Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Mandal, Swagata; Paul, Rourab; Sau, Suman; Chakrabarti, Amlan; Chattopadhyay, S.

doi:10.1016/j.micpro.2016.12.003

Cited by 6 publications

(7 citation statements)

References 38 publications

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“…With the increase of redundant bits, error detection capability of the methods proposed in [10], [11] increase, whereas in our case error detection is always 100% with very less number of redundant bits as illustrated in Table II. During scrubbing, all configuration frames need to be downloaded.…”

mentioning

confidence: 60%

“…As there is only one downloading port is available in the Internal Configuration Access Port (ICAP) proper port scheduling is also necessary to download n tasks in m PRR (n≥m) as described by authors in [16] for hard real time reconfiguration system. Authors proposed a method which integrates error detection and correction with dynamic priority based hardware scheduling in [10] but here tasks are periodic in nature and criticality of the tasks are not included. Unlike to the previous case, here our proposed soft error mitigation for aperiodic tasks calculates the priority for reconfiguration of tasks considering its criticality, execution time and area.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Problem of storing the golden copy can be solved by using different error detection and correction (EDAC) codes like Bose, Chaudhuri, Hocquenghem (BCH) [9] code for error mitigation in configuration data but their decoding complexity and latency are quite high. In general, soft errors are localized in nature i.e it corrupts adjacent multiple bits [10] and hence, complicated EDAC with high redundancies are required to efficiently correct the effect of adjacent erroneous bits. Sometimes concatenated code or product code may be good solutions for mitigation of adjacent MBU (AMBU) as it corrects data along both row and column of storage element in parallel.…”

Section: Introductionmentioning

confidence: 99%

“…Generally, both of the attributes bring positive effect on the throughput performance. Table II compares error detection capability of the SHA-3 with other error detection methods proposed in [10], [11] where authors have used parity with interleaving along different dimensions of CM for error detection. Here we have considered ten tasks in CM and each has hundred configuration frames.…”

mentioning

confidence: 99%

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Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

Mandal¹,

Sarkar

Ming³

et al. 2019

2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)

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Efficient low complexity error correcting code (ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory (CM) of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper, we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliability.

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confidence: 60%

Section: Literature Reviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

Mandal¹,

Sarkar

Ming³

et al. 2019

2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)

Self Cite

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“…These ad-hoc techniques can be divided into Algorithmic-Based Fault-Tolerance Techniques (ABFT), in which the error detection is achieved by exploiting arithmetic properties of the algorithm [19], [20], and techniques based on exploiting structural properties of the design to create a protection scheme [16]. Other approaches, which are out of the scope of this paper, are based on analog circuits that give support to digital designs to detect faulty behaviors [21] and powerful error correction codes to protect the FPGA hardware from soft errors, which involve iterative processes at a larger timing cost [22], [23].…”

Section: Introductionmentioning

confidence: 99%

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

et al. 2020

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The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.

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Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique

Vlagkoulis,

Sari,

Proko

et al. 2019

2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Cited by 6 publications

References 38 publications

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique

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