Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA

Abstract

Efficient low complexity error correcting code (ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory (CM) of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper, we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliability.

Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper

“…However, as shown in Figure 11, Sahoo et al [110,111] proposed a hardware/hardware partitioning methodology that allows using application specific heterogeneous PRRs, that provided the scope for improving both the latency (average makespan) and reliability (MTTF) in DPR-based systems. A few papers such as [112][113][114][115][116], have addressed reconfigurable processors in a system with different criticality tasks to improve timing reliability. In [112,113], Santos, et al have proposed a new efficient scrubbing mechanism to increase the system's reliability by considering the criticality and timing of the hardware task execution.…”

“…Ref. [116] have detected an error by using the Secure Hash Algorithm and corrected them by using parity based two-dimensional erasure code, while the performance is reduced, which consists of time error detection and correction. This method has taken the execution period and criticality into account to correct faulty data.…”

Design Space Exploration and Resource Management of Multi/Many-Core Systems

“…A few papers such as [112][113][114][115][116], have addressed reconfigurable processors in a system with different criticality tasks to improve timing reliability. In [112,113], Santos, et al have proposed a new efficient scrubbing mechanism to increase the system's reliability by considering the criticality and timing of the hardware task execution.…”

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs

“…Recently, because of their reconfigurability, field programmable gate arrays (FPGAs) are used frequently for space embedded systems [1], [2], [3]. Using FPGAs, since the hardware's specification can be changed easily, the lifetime of space systems can be extended while maintaining the latest functions.…”