Efficient Dual-Rail Implementations in FPGA Using Block RAMs

Bhasin, Shivam; Guilley, Sylvain; Souissi, Youssef; Graba, Tarik; Danger, Jean‐Luc

doi:10.1109/reconfig.2011.32

Cited by 13 publications

(22 citation statements)

References 9 publications

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“…On the other hand, when the platform is fixed, routing techniques can be applied to improve BCDL. As demonstrated in [13], the reduction of fan-out improves the robustness of BCDL implementations. Whereas, low fan-out circuit still has some leakage present which can be exploited by a stronger attacker.…”

Section: Pre-place Arrangement For Bcdlmentioning

confidence: 95%

“…In this article, we aim to have verifications of the routing impact for a secure balanced cell-based dual-rail logic (BCDL) [13] implemented AES core with strict dual-rail networks. This work depends on two properties:…”

Section: C(t) > C (F)) the Charged Energy E(t)-c(t) Is Different Fromentioning

confidence: 99%

“…For instance, using the embedded block BRAM, complex functions like an AES substitution box can be easily implemented. In addition, configurable logic block (CLB) in Xilinx series can efficiently implement a two-stage BCDL cell at minimum overhead [13]. Thus, Virtex-5 family possess LUT6 which can be used as one 6-input 1-output LUT or two 5-input 1-output LUT.…”

Section: Early Propagation Pitfallmentioning

confidence: 99%

“…Owing to the imbalance between the true and false parts in real implementation, some leakage is inevitably present. We assume this leakage to be slightly related to Hamming weight model given the construction of circuit and two-phase operation [13]. In this case study, MIA is preferably to be used since it can reveal weak information leakage and find both linear and non-linear dependencies between the model and leakage.…”

Section: Mia Test Analysismentioning

confidence: 99%

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Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Bhasin

Otero

et al. 2015

IET Information Security

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Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

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Section: Pre-place Arrangement For Bcdlmentioning

confidence: 95%

Section: C(t) > C (F)) the Charged Energy E(t)-c(t) Is Different Fromentioning

confidence: 99%

Section: Early Propagation Pitfallmentioning

confidence: 99%

Section: Mia Test Analysismentioning

confidence: 99%

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Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Bhasin

Otero

et al. 2015

IET Information Security

Self Cite

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“…However, both SDDL and BCDL do suffer from routing imbalance and therefore need back-end techniques for balancing the dual rail. AES with T-tables reduces the fanout, which in a way reduces routing imbalance and makes back-end balancing easier [Bhasin et al 2011]. …”

Section: Dpl and The Use Of Brammentioning

confidence: 99%

Exploiting FPGA Block Memories for Protected Cryptographic Implementations

Bhasin

Danger

Guilley

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2×) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.

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Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

2020

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The effort in reducing the area of AES implementations has largely been focused on application-specific integrated circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on field-programmable gate arrays (FPGAs). A similar discrepancy holds for masking schemes-a well-known side-channel analysis countermeasure-which are commonly optimized to achieve minimal area in ASICs. In this paper, we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction in the area footprint on FPGA devices. We present new AES implementations which improve on the state-of-the-art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Güneysu at ASAP 2016. We further explore the protection of such implementations against side-channel attacks. We introduce a generic methodology for masking any n-bit Boolean functions of degree t with protection order d. The methodology is exact for first-order and heuristic for higher orders. Its application to our new construction of the AES S-box allows us to improve previous results and introduce the smallest first-order masked AES implementation on Xilinx FPGAs, to date.

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Efficient Dual-Rail Implementations in FPGA Using Block RAMs

Cited by 13 publications

References 9 publications

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Exploiting FPGA Block Memories for Protected Cryptographic Implementations

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version

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