Efficient DSP implementation of an LDPC decoder

In this paper we propose a new combinational criterion as a mean for comparison between different LDPC codes in terms of complexity and efficiency. The main idea behind the proposed criterion is to merge different aspects of a code to a unique number. We will show that the new criterion, named "Goodness Number" or GN, is applicable, and in some circumstances it is preferred to other criteria such as complexity and error probability criteria and at the same time it maintains computational simplicity 1 .

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“…Usually this number is set to 10 iterations [7]. In this example we will show that this choice is adequate, through two different approaches.…”

Section: D-determining the Stopping Criterionmentioning

confidence: 99%

A new criterion to compare different LDPC codes for hardware implementation

Torbati

Attari

Moosavinia

2008

2008 Canadian Conference on Electrical and Computer Engineering

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“…However serial architectures did not receive much attention, due to the fact that the sequential processing does not achieve large throughput. This solution is particularly suitable for software implementations on Digital Signal Processors [9] . As throughput requirements in WNs applications are usually much lower than in wireless communications, the serial approach appears as the best solution to implement low cost and low energy decoding in a sensor node.…”

Section: Introductionmentioning

confidence: 99%

LDPC Architecture for Improved BER in Wireless Networks

M¹

2013

IJCA

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To achieve high throughput in wireless networks a partial parallel LDPC decoder is proposed in this paper. For fullyparallel decoders, it suffers from large hardware complexity caused by a large set of processing units and complex interconnections. In wireless networks coding complexity and routing congestion can be reduced by designing the decoder with partially-parallel architecture. The partially-parallel architecture with Split Row algorithm reduces the total global wire length by about 26% without any hardware overhead and increasing the throughput by 60% and 71% in wireless networks.

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“…The huge computation and high throughput requirements make it very difficult to implement a high throughput LDPC decoder on a general purpose DSP. For example, a 5.4 Mbps LDPC decoder was implemented on TMS320C64xx DSP running at 600 MHz [29]. This throughput performance is not enough to support high data rates defined in new wireless standards.…”

Section: Ldpc Decoder Accelerator Architecturementioning

confidence: 99%

Application-Specific Accelerators for Communications

Sun

Amiri

Brogioli³

et al. 2010

Handbook of Signal Processing Systems

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For computation-intensive digital signal processing algorithms, complexity is exceeding the processing capabilities of general-purpose digital signal processors (DSPs). In some of these applications, DSP hardware accelerators have been widely used to off-load a variety of algorithms from the main DSP host, including FFT, FIR/IIR filters, multiple-input multiple-output (MIMO) detectors, and error correction codes (Viterbi, Turbo, LDPC) decoders. Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient. However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator. First, these algorithms should have data-parallel computations and repeated operations that are amenable to hardware implementation. Second, these algorithms should have a deterministic dataflow graph that maps to parallel datapaths. The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power. In this chapter, we focus on some of the basic and advanced digital signal processing algorithms for communications and cover major examples of DSP accelerators for communications.

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Efficient DSP implementation of an LDPC decoder

Cited by 20 publications

References 5 publications

A new criterion to compare different LDPC codes for hardware implementation

A new criterion to compare different LDPC codes for hardware implementation

LDPC Architecture for Improved BER in Wireless Networks

Application-Specific Accelerators for Communications

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