Efficient driving-capability programmable frequency divider with a wide division ratio range

Zhang, Mo; Islam, Syed K.; Haider, Mohammad Rafiqul

doi:10.1049/iet-cds:20070150

Cited by 8 publications

(9 citation statements)

References 10 publications

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“…The Mo signals from the on-edge 2/3 cell and the previous ones have the desired frequency f in /DR, it is similar to [8]. From the Eq.…”

Section: Design Of the Proposed Dividermentioning

confidence: 88%

“…When the division ratios are 2 n À 1, the duty-cycle is k=ð2k þ 1Þ, where 2k þ 1 ¼ 2 n À 1. This is equal to the Solution 2 in [8].…”

Section: Design Of the Proposed Dividermentioning

confidence: 96%

“…3 (Div_Vaucher), which greatly extended the range of the division ratio. The drawback of the design is its narrow output pulse width, the driving capability is therefore limited, and even by adding a dutycycle corrector [5][6][7] at the divider's output can not solve the problem [8].…”

Section: Introductionmentioning

confidence: 99%

“…An improved structure was also presented in [8], it combined two solutions to obtain close-to 50% duty-cycle, but the structure is a bit complicated. This may reduce the divider's flexibility and require much additional layout effort.…”

Section: Introductionmentioning

confidence: 99%

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A wide division-ratio range programmable frequency divider with driving-capability improved

Wang

Zhang

et al. 2010

Analog Integr Circ Sig Process

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This letter presents an improved architecture of wide division ratio range programmable frequency divider with driving-capability improved. The proposed architecture combines the traditional 2/3 cells and the revised ones to retain the high speed feature and broaden the output duty-cycle. Only less OR and AND gates are added to select the proper output. All of the added circuits are operating at the lower frequency. Thus it enhances the divider's driving-capability with almost adding no power consumption. This improvement makes it applicable to drive various clocked circuits, which need different frequencies. The presented equation can be used to predict the output duty-cycle with the expected division ratio accurately. Test results show that the output duty-cycle is between 33 and 66%, which corroborate the calculations.

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“…The Mo signals from the on-edge 2/3 cell and the previous ones have the desired frequency f in /DR, it is similar to [8]. From the Eq.…”

Section: Design Of the Proposed Dividermentioning

confidence: 88%

“…When the division ratios are 2 n À 1, the duty-cycle is k=ð2k þ 1Þ, where 2k þ 1 ¼ 2 n À 1. This is equal to the Solution 2 in [8].…”

Section: Design Of the Proposed Dividermentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A wide division-ratio range programmable frequency divider with driving-capability improved

Wang

Zhang

et al. 2010

Analog Integr Circ Sig Process

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“…An improved design has been reported by our group in [17] to accommodate this option which has not been used in the proposed PLL design. With the proposed method used in this paper, the output pulse width of the fractional programmable divider is greatly improved with a little increment of power consumption.…”

Section: Design Of the Programmable Fractional Dividermentioning

confidence: 99%

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

Zhang

Haider

Islam

et al. 2010

Analog Integr Circ Sig Process

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The prolific growth of portable electronic devices (PED) has generated tremendous interests among researchers to develop programmable phase-locked loops (PLLs) because of their abilities to produce multiple spectrally pure output frequencies from a fixed frequency oscillator. The power consumption of the RF block of a PED is mostly dominated by the programmable PLLs which are widely used in the design of these devices. Therefore to reduce the overall power consumption in a portable device and to increase the battery life time, lowvoltage and low-power are the two key requirements for the PLL design. In this work an improved programmable fractional frequency divider has been incorporated to enhance the overall performance of the PLL that includes lower operating supply voltage and lower power consumption compared to the state-of-art. The proposed programmable fractional PLL has an operating frequency in the range of 1.7-2.5 GHz, and a frequency resolution of 2.5 MHz. Measurement results reveal that the proposed programmable PLL can operate at 2.4 GHz with a 1.46 V power supply voltage and only 10 mW of power consumption.

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A low-area full-division-range programmable frequency divider with a 50% duty-cycle output

Tsai

2013

Microelectronics Journal

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Efficient driving-capability programmable frequency divider with a wide division ratio range

Cited by 8 publications

References 10 publications

A wide division-ratio range programmable frequency divider with driving-capability improved

A wide division-ratio range programmable frequency divider with driving-capability improved

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

A low-area full-division-range programmable frequency divider with a 50% duty-cycle output

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