Efficient digital baseline wander algorithm and its architect u re for fast ethernet

Baek, Jehyun; Hong, Jin-Gi; SunWoo, Myung-Hoon; Kim, K.U.

doi:10.1109/sips.2004.1363038

Cited by 6 publications

(2 citation statements)

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“…This paper proposes a DSP unit [17][18][19] consisting of a PGA, timing recovery loop, the proposed adaptive equalizer, and the new BLW corrector for fast Ethernet. The proposed DSP unit is implemented in the digital domain, except for the PLL and amplifier.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed DSP unit [17][18][19] improves the mean square error (MSE) by about 1 dB compared with the existing architecture [16]. The measured BER is less than 10 −10 , as specified in the standard [1], when the cable length is 150 m. The proposed DSP unit can track the optimum phase in all channels with lengths ranging from 0 m to 150 m. Moreover, the proposed DSP unit can be used as a 1000Base-TX Gigabit Ethernet receiver that consists of four 100Base-TX receivers in parallel.…”

Section: Introductionmentioning

confidence: 99%

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Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

Hong

Baek

Sunwoo

2009

J Sign Process Syst

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This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2 −7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10 −10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%