Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Sasikala, S.; Murugesan, G.

doi:10.1504/ijbet.2017.082672

Cited by 9 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An N-tap FIR filter obtained from an input sequence x(n) of infinite length sequence and the impulse sequence h(n) of length N, in z-domain as [15] (…”

Section: Formulation Of Traditional Parallel Fir Filters Using Polyphase Decompostionmentioning

confidence: 99%

“…Developing small size parallel FIR filters and then cascading it to build large ones is a solution [6]. L-parallel filter using approximately (2L-1) subfilter blocks can be implemented, each of which is of length N/L usingFast FIR algorithms (FFAs) [15] . There is an advantage when FFA structures are used.…”

Section: Introductionmentioning

confidence: 99%

“…The reduction in area is achieved by the implementation of FFA .Many High Level transformations have been used to design several VLSI Architectures. [6][7] [13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of Low Area and High Speed Parallel FIR Digital Filter using Fast FIR Algorithm

Gomathi¹

2020

IJETER

View full text Add to dashboard Cite

Finite Impulse Response (FIR) is thought to be one amongst the most important operations in digital signal processing. Parallel FIR filter has various applications in video compression and equalizers. Implementation of traditional parallel FIR filter offers high speed at the expense of increased hardware by the block size. This huge hardware penalty can't be tolerated in many design situation. So, it's necessary to style parallel FIR filter structures that is implemented with low area than traditional block FIR filtering structures. This paper addresses the design of higher order Parallel FIR filters using small sized filters using FFA algorithm. The Parallel Fast FIR Algorithm specially targets within the sharing of filter coefficients .The Parallel Fast FIR algorithm gives the output with delay of 13.0825 ns which is 47 you quicker than Parallel FIR Algorithm which produces the output with delay of 17.9675 ns. The Parallel Fast FIR Algorithm has been implemented in Four tap , Eight tap FIR filter and sixteen tap FIR filter yet in Parallel FIR Algorithm and Traditional FIR algorithm.

show abstract

“…An N-tap FIR filter obtained from an input sequence x(n) of infinite length sequence and the impulse sequence h(n) of length N, in z-domain as [15] (…”

Section: Formulation Of Traditional Parallel Fir Filters Using Polyphase Decompostionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of Low Area and High Speed Parallel FIR Digital Filter using Fast FIR Algorithm

Gomathi¹

2020

IJETER

View full text Add to dashboard Cite

show abstract

“…The present VLSI 2-D DWT architectures be able to classify into convolution-based designs [3]- [11] and lifting-based designs [12]- [32]. Few architectures sort from greatly parallel to programmable DSP-based architectures to folded architectures [16] and [17]. Among this, FIR filter banks are used in the implementation of convolution based architectures whereas factorizing the filter banks into more than a few lifting steps is adapted in the implementation of the lifting-based architectures [28].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Efficient Architecture of Fine Grain Pipelined Lifting Scheme Based Two Dimensional Discrete Wavelet Transform

V*¹,

Geetha²,

Murugesan³

2019

IJITEE

View full text Add to dashboard Cite

Many Discrete Wavelet Transform (DWT) based VLSI architectures have been projected to meet the necessities of the synchronized signal processing. It includes image processing, speech processing, signal and video processing, etc. The practical implementation of DWT has fewer hitches in terms of hardware complexity and memory requirement since it needs to process huge volume of data. The traditional convolution based system needs more multipliers and larger memory and is also not suitable to provide speed or power efficient image or video processing designs. The lifting scheme involves very few mathematical computations compared to the convolution-based DWT. In this paper, we propose an architecture that performs Discrete Wavelet Transform (DWT) using a lifting-based scheme with fine grained pipelined architecture. The basic DWT filters used in image compression are 5/3(lossless) and 9/7(lossy) filters. In fine grain pipelining, multiplier is split into two units by placing the latches on the horizontal cutset across the multiplier. Thus the critical path is reduced to half of the multiplier delay. As a result, it is a speed efficient architecture and is symmetrical with a lower hardware complexity. The architecture is designed using verilog HDL and implemented on Xilinx Spartan 3E FPGA.

show abstract

Hardware Implementation of a High-Speed Adaptive Filter Using a Combination of Systolic and Convex Architectures

Thannoon,

Hashim

2023

Circuits Syst Signal Process

View full text Add to dashboard Cite

Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals

Cited by 9 publications

References 0 publications

Design of Low Area and High Speed Parallel FIR Digital Filter using Fast FIR Algorithm

Design of Low Area and High Speed Parallel FIR Digital Filter using Fast FIR Algorithm

Implementation of Efficient Architecture of Fine Grain Pipelined Lifting Scheme Based Two Dimensional Discrete Wavelet Transform

Hardware Implementation of a High-Speed Adaptive Filter Using a Combination of Systolic and Convex Architectures

Contact Info

Product

Resources

About