Efficient design of fault tolerant tiles in QCA

Sen, Bibhash; Agarwal, Aman; Nath, Rajdeep Kumar; Mukherjee, Rijoy; Sikdar, Biplab K.

doi:10.1109/indicon.2014.7030690

Cited by 12 publications

(9 citation statements)

References 9 publications

(12 reference statements)

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“…The energy dissipation thermal display of the proposed fault‐tolerant structure and existing fault‐tolerant three‐input majority gates in previous studies are illustrated in Figure . As can be seen in Figure , it should be noted that high‐power cells generate a lot of heat in which hot spots appear in darker colors.…”

Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

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A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

Ahmadpour

Mosleh

2019

Concurrency and Computation

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Quantum-dot cellular automata (QCA) is a very interesting nanoscale technology. Ultradense structure and ultralow power consumption are the most important features of QCA compared to CMOS. QCA circuits often suffer from various types of manufacturing defects and are therefore prone to fault. Hence, the design of fault-tolerant circuits in QCA technology is considered a necessity. In this paper, a novel fault-tolerant three-input majority gate is presented using 12 simple and rotated cells in QCA technology. The proposed structure is investigated against all kinds of cell omission, extra-cell deposition, and cell displacement defects. The simulation results are verified by QCADesigner 2.0.3, and it showed 100%, 89.29%, and 100% tolerance against single-cell omission, double-cell omission, and extra-cell deposition, respectively. In addition, the proposed structure is robust against cell displacement defects. Finally, using the proposed structure, a novel coplanar full adder is presented. The results were compared and indicated that the proposed designs are more reliable than the existing designs. Furthermore, QCAPro power estimator tool was employed to estimate the energy dissipation of the proposed structure. KEYWORDSfault-tolerant, nanotechnology, quantum-dot cellular automata (QCA), three-input majority gate INTRODUCTIONIn the near future, complementary metal-oxide-semiconductor (CMOS) technology is expected to reach the end of its way due to limitations such as switching speed, scaling specifications, high cost of lithography, and thermal challenges. 1-3 CMOS technology also suffers from lower tolerability and manufacturing diversity, which have a negative impact on the reliability of these devices, leading to an increase in the number of faults. Future CMOS constraints have led many researchers to design nanoscale devices. 4 Quantum-dot cellular automata (QCA) has appeared as a favorable new innovation for future integrated circuit generation, which can overcome CMOS constraints. 3 The simplest element in QCA technology is a square cell with four quantum dots located in its four corners. The transfer of information takes place by columbic interactions between the fundamental elements (cells) instead of electrical current. [3][4][5] Up to now, extensive attempts have been made on the design of various digital circuits such as multipliers, 6-8 adders, 9-19 memory devices, 20-23 arithmetic and logic unit, 24 and multiplexers [25][26][27][28][29] in QCA technology, but according to a conducted study by Bahar et al, 30 the high complexity of nanocircuit structures results in the need to design high fault-tolerant structures. The QCA technology encounters with a variety of manufacturing defects such as extra-cell deposition, cell omission, cell displacement, or cell misalignment that make QCA circuits unusable. 31,32 A three-input majority gate is considered one of the main basic gate in the QCA circuits. 33,34 Providing robust structures for the majority gate will result in the creation of fault-tolerant logic cir...

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Section: The Proposed Fault‐tolerant Circuitsmentioning

confidence: 99%

“…A fault‐tolerant three‐input majority gate with 27 cells has been introduced by Sen et al In this structure, rotated and normal cells have been used, which has 95% and 78% tolerance against single‐cell and double‐cell omission defects, respectively.…”

Section: Introductionmentioning

confidence: 99%

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

Ahmadpour

Mosleh

2019

Concurrency and Computation

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“…Moreover, the fault-tolerance of the TMR system strongly depends on the fault-tolerance capability of the majority gate. Use of a fault-tolerant majority gate [22] may add up more overhead (22 more cells). The situation become even worse in the case of NAND multiplexing and majority multiplexing.…”

Section: Applicability Of Generic Fault-tolerant Schemes On Existing mentioning

confidence: 99%

“…Ma et al [10] presented a comparative study on the applicability of a few generic fault-tolerant schemes such as triple modular redundancy (TMR) [15], NAND multiplexing [16], and majority multiplexing [17] in the context of reliable realization of QCA systems. A few new fault-tolerant QCA designs of majority gates and adders have been reported in the literature [18,19,20,21,22].…”

Section: Introductionmentioning

confidence: 99%

On fault-tolerant design of Exclusive-OR gates in QCA

2017

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Design paradigms of logic circuits with Quantum-dot Cellular Automata (QCA) have been extensively studied in the recent past. Unfortunately, due to the lack of mature fabrication support, QCA-based circuits often suffer from various types of manufacturing defects and variations, and therefore, are unreliable and error-prone. QCA-based Exclusive-OR (XOR) gates are frequently used in the construction of several computing subsystems such as adders, linear feedback shift registers, parity generators and checkers. However, none of the existing designs for QCA XOR gates have considered the issue of ensuring fault-tolerance. Simulation results also show that these designs can hardly tolerate any fault. We investigate the applicability of various existing fault-tolerant schemes such as triple modular redundancy (TMR), NAND multiplexing, and majority multiplexing in the context of practical realization of QCA XOR gate. Our investigations reveal that these techniques incur prohibitively large area and delay and hence, they are unsuitable for practical scenarios. We propose here realistic designs of QCA XOR gates (in terms of area and delay) with significantly high fault-tolerance against all types of cell misplacement defects such as cell omission, cell displacement, cell misalignment and extra/additional cell deposition. Furthermore, the absence of any crossing in the proposed designs facilitates low-cost fabrication of such systems.

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“…In most of the QCA-based XOR and adder designs, the performance of circuits has been computed in terms of generalised parameters. Only a few researchers considered fault tolerance as one of the design metrics in their designs of QCA-based circuits [27][28][29][30][31][32][33][34][35][36] to date. So, there is emerging need to develop methods which involve less area and delay overheads to improve the fault tolerance of digital circuits.…”

Section: Introductionmentioning

confidence: 99%

Fault‐tolerant design and analysis of QCA‐based circuits

Singh

Raj

Sarin

2018

IET Circuits, Devices & Systems

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Emerging nanoscale computing structure quantum-dot cellular automata (QCA) is evolving as a possible replacement for complementary metal-oxide-semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication-related faults and process variations. So, QCA-based circuits are prone to errors, and therefore pose significant reliability-related issues. Hence, there is an emerging need to design fault-tolerant QCA-based circuits to mitigate the reliability issues. This study first presents QCA-based new designs of 2-input Exclusive-OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault-tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault-tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault-tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault-tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool.

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Efficient design of fault tolerant tiles in QCA

Cited by 12 publications

References 9 publications

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

A novel ultra‐dense and low‐power structure for fault‐tolerant three‐input majority gate in QCA technology

On fault-tolerant design of Exclusive-OR gates in QCA

Fault‐tolerant design and analysis of QCA‐based circuits

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