Efficient DAG construction and heuristic calculation for instruction scheduling

Smotherman, Mark; Krishnamurthy, Sanjay; Aravind, P.; Hunnicutt, David

doi:10.1145/123465.123482

Cited by 22 publications

(15 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Such a heuristic usually consists of a set of features and a priority or order in which to test the features. Many possible features and orderings have been proposed (see, for example, Blainey 1994;Smotherman et al 1991). The heuristic in a production compiler is usually hand-crafted by choosing and testing many different subsets of features and different possible orderings-a potentially time-consuming process.…”

Section: Introductionmentioning

confidence: 99%

Learning heuristics for basic block instruction scheduling

et al. 2007

View full text Add to dashboard Cite

Instruction scheduling is an important step for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction scheduling is to find a minimum length schedule for a basic block-a straightline sequence of code with a single entry point and a single exit point-subject to precedence, latency, and resource constraints. Solving the problem exactly is known to be difficult, and most compilers use a greedy list scheduling algorithm coupled with a heuristic. The heuristic is usually hand-crafted, a potentially time-consuming process. In contrast, we present a study on automatically learning good heuristics using techniques from machine learning. In our study, a recently proposed optimal basic block scheduler was used to generate the machine learning training data. A decision tree learning algorithm was then used to induce a simple heuristic from the training data. The automatically constructed decision tree heuristic was compared against a popular critical-path heuristic on the SPEC 2000 benchmarks. On this benchmark suite, the decision tree heuristic reduced the number of basic blocks that were not optimally scheduled by up to 55% compared to the critical-path heuristic, and gave improved performance guarantees in terms of the worst-case factor from optimality.

show abstract

Section: Introductionmentioning

confidence: 99%

Learning heuristics for basic block instruction scheduling

et al. 2007

View full text Add to dashboard Cite

show abstract

“…Our implementation uses a list scheduler but other schedulers can be used as long as they provide a deterministic result. From the many available list-scheduler heuristics [30], we selected the dependency height as the main criterion and we prioritize loadoperations in order to increase the scheduler's freedom for scheduling shorter sequences. We found that using this combination of instruction selection criteria we can obtain a high quality result 1 without increasing the computational complexity.…”

Section: B Experimental Resultsmentioning

confidence: 99%

Exploring processor parallelism: Estimation methods and optimization strategies

Jordans

Corvino

Jóźwiak

et al. 2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

View full text Add to dashboard Cite

Abstract-Automatic optimization of application-specific instruction-set processor (ASIP) architectures mostly focuses on the internal memory hierarchy design, or the extension of reduced instruction-set architectures with complex custom operations. This paper focuses on very long instruction word (VLIW) architectures and, more specifically, on automating the selection of an application specific VLIW issue-width. The issuewidth selection strongly influences all the important processor properties (e.g. processing speed, silicon area, and power consumption). Therefore, an accurate and efficient issue-width estimation and optimization are some of the most important aspects of VLIW ASIP design. In this paper, we first compare different methods for the estimation of required the issue-width, and subsequently introduce a new force-based parallelism estimation method which is capable of estimating the required issue-width with only 3% error on average. Furthermore, we present and compare two techniques for estimating the required issue-width of software pipelined loop kernels and show that a simple utilization-based measure provides an error margin of less than 1% on average.

show abstract

“…The pre-scheduling steps such as the construction of dependence graphs are also examined in [12]. A reservation table, which was originally developed in the context of designing hardware pipelines [13], represents resource constraints during scheduling.…”

Section: Related Workmentioning

confidence: 99%

Efficient backtracking instruction schedulers

Abraham

Meleis

Baev

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

View full text Add to dashboard Cite

Current schedulers for acyclic regions schedule operations in dependence order and never revisit or undo a scheduling decision on any operation. In contrast, backtracking schedulers may unschedule already scheduled operations, in order to make space for the operation currently being scheduled. Backtracking schedulers have the potential for generating better schedules, e.g. more effectively filling branch delay slots, but are more compile-time intensive and therefore, not considered practical for production use.In this report, we first describe conventional cycle and list schedulers followed by two novel backtracking schedulers. The full-backtracking OperBT scheduler enables backtracking for all operations and unschedules already scheduled operations to make space for the current operation, if, among other situations, there is no available slot that satisfies dependence constraints. This scheduler is effective in generating high quality schedules that for instance, successfully fill branch delay slots but likely backtracks too often. The selective backtracking ListBT scheduler enables backtracking only when scheduling certain types of operations, for which backtracking is likely to be advantageous, e.g. branches. When not scheduling these operations (or operations that were displaced through backtracking), the scheduler reverts to efficient scheduling in dependence order. The ListBT scheduler backtracks less often than the OperBT scheduler. Both schedulers successfully fill a large fraction of the branch delay slots and improve performance of the scheduled code significantly.

show abstract

Efficient DAG construction and heuristic calculation for instruction scheduling

Cited by 22 publications

References 11 publications

Learning heuristics for basic block instruction scheduling

Learning heuristics for basic block instruction scheduling

Exploring processor parallelism: Estimation methods and optimization strategies

Efficient backtracking instruction schedulers

Contact Info

Product

Resources

About