Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations

Abolmaali, Sheis; Mansouri-Ghiasi, Nika; Kamal, Mehdi; Afzali-Kusha, Ali; Pedram, Massoud

doi:10.1109/tvlsi.2017.2703623

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…The industry's mainstream electronic design automation (EDA) tool for logic synthesis is Design Compiler (DC) produced by Synopsys5. Timing optimization algorithms for logic circuits have been integrated in DC and have been demonstrated to reduce critical path delays significantly [5,6]. Figure 1 illustrates the positioning of logic circuits (represented by ellipses) between flip-flops FF1 and FF2 of a pipeline circuit [7,8], where the logic circuits generally employ multiple inputs and outputs.…”

Section: Introductionmentioning

confidence: 99%

Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

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Section: Introductionmentioning

confidence: 99%

Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders

Papachatzopoulos

Paliouras

2019

IEEE Trans. Circuits Syst. I

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An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space

Abolmaali

Kamal

Afzali-Kusha

et al. 2018

ACM Trans. Des. Autom. Electron. Syst.

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In this article, we present a critical path selection method that efficiently finds true (sensitizable) critical paths of a circuit in the presence of process variations. The method, which is based on the viability analysis, tries to select the least number of true critical paths that cover all of circuit critical gates. Critical gates are those that make a path critical with a probability higher than a predefined threshold value. Selecting fewer critical paths leads to less computation time for the algorithm and shorter test time of fabricated chips. For this purpose, an efficient Statistical Static Timing Analysis– (SSTA) based technique is suggested. This technique tries to find circuit-critical gates whose process parameter variations cover a major part of the process space. Improving the process space coverage using fewer paths is achieved by considering both spatial (proximity of gates) and structural (having common gates) correlations in the analysis of choosing the critical paths. In the selection process, paths with low similarities in their characteristics are preferred. In addition, only true paths whose delays affect the maximum delay of the circuit are included. The selected paths can be used in the test process of the fabricated chips to determine if the chip meets its timing requirements. Also, a modified viability analysis that incorporates statistical computations is used in the SSTA. The efficacy of the proposed method is evaluated by comparing its results for combinational and sequential ISCAS benchmarks with those obtained by exhaustive search. Results indicate although, on average, only 4.38% of all the critical paths found by the exhaustive search are selected by the proposed method, the maximum probability of criticality for the paths that are not considered in our method is, on average, less than 4%.

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Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations

Cited by 3 publications

References 8 publications

Novel Verification Method for Timing Optimization Based on DPSO

Novel Verification Method for Timing Optimization Based on DPSO

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders

An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space

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