Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

Bekooij, Marco; Smit, Gerard J. M.; Jansen, P.G.; Wiggers, Maarten H.

doi:10.1145/1176254.1176260

Cited by 45 publications

(38 citation statements)

References 12 publications

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“…This point can be proved easily from the Integer Linear System Π(K). It was also noticed experimentally by [22]. …”

Section: Examplesupporting

confidence: 64%

“…This limitation on the structure of G was extensively studied by many authors and corresponds to most of the applications (see. as example [22], [20], [21]). …”

Section: B Consequence For a Symmetric Mwteg Without Circuits Of Mormentioning

confidence: 99%

“…More recently, in [20], [21] authors have dealed with this problem with throughput constraint based on a state space exploration with model checking techniques. Lastly, Wiggers et al [22] developed a heuristic that aims to build a periodic firings of the transitions that minimizes the buffer capacities of a SDF.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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A new approach for minimizing buffer capacities with throughput constraint for embedded system design

Benazouz

Marchetti

Munier-Kordon

et al. 2010

ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010

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Abstract-The design of streaming (e.g. multimedia or network packet processing) applications must consider several optimizations such as the mimimization of the whole surface of the memory needed on a Chip. The minimum throughput of the output is usually fixed. In this paper, we present an original methodology to solve this problem.The application is modelled using a Marked Timed Weighted Event Graphs (in short MTWEG), which is a subclass of Petri nets. Transitions correspond to specific treatments and the places model buffers for data transfers. It is assumed that transitions are periodically fired with a fixed throughput.The problem is first mathematically modelled using an Integer Linear Program. We then study for a unique buffer the optimum throughput according to the capacity. A first polynomial simple algorithm computing the minimum surface for a fixed throughput is derived when there is no circuit in the initial MTWEG, which corresponds to a wide class of applications. We prove in this case that the capacities of every buffer may be optimized independently.For general MTWEG, the problem is NP-Hard and an original polynomial 2-approximation algorithm is presented. For practical applications, the solution computed is very close to the optimum.

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“…This point can be proved easily from the Integer Linear System Π(K). It was also noticed experimentally by [22]. …”

Section: Examplesupporting

confidence: 64%

“…This limitation on the structure of G was extensively studied by many authors and corresponds to most of the applications (see. as example [22], [20], [21]). …”

Section: B Consequence For a Symmetric Mwteg Without Circuits Of Mormentioning

confidence: 99%

See 1 more Smart Citation

A new approach for minimizing buffer capacities with throughput constraint for embedded system design

Benazouz

Marchetti

Munier-Kordon

et al. 2010

ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010

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“…Once the firing rule is satisfied, an actor executes its entire body without blocking. Different variants of dataflow models exist, e.g., Static Dataflow (SDF), Cyclo-Static Dataflow (CSDF) [17], Variable Rate Dataflow (VRD) [18], some of which are analyzable. This means that existing formalisms [19] can derive an end-to-end latency and throughput of an application, given the worst case timing of each of its actors.…”

Section: Application Models Of Computationmentioning

confidence: 99%

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Nejad

Molnos

Goossens

2011

2011 14th Euromicro Conference on Digital System Design

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Abstract-Multi-processor Systems on Chip (MPSoCs) execute multiple applications concurrently. These applications may belong to different domains, i.e., may have firm-, soft-, or non-realtime requirements. A composable system simplifies system design, integration, and verification by avoiding the inter-application interference. Existing work demonstrates composability for applications expressed using a single model of computation. For example, Kahn Process Network (KPN) and dataflow are two common data-driven parallel models of computation, each with different properties and suited for different application domains. This paper extends existing work with support for concurrent, composable execution of KPN and dataflow applications on the same MPSoC platform. We formalize a unified execution model by defining its operations that implement the different models of computation on the MPSoC, and discuss the trade-offs involved. Our experiments indicate that multiple applications modeled in KPN and dataflow run composably on an MPSoC platform.

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“…Wiggers [13] presents an algorithm with linear computational complexity to determine close-to-minimum buffer capacities for a given throughput constraint. However, this approach imposes a form of strictly periodic scheduling that requires a counter in every functional block, which leads to resource overhead in FPGA and other hardware-oriented implementations.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

Kee

Bhattacharyya

Kornerup

2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flowgraph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed techinque is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design.

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Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure

Cited by 45 publications

References 12 publications

A new approach for minimizing buffer capacities with throughput constraint for embedded system design

A new approach for minimizing buffer capacities with throughput constraint for embedded system design

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

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