Efficient bus arbitration protocol for SoC design

Gupta, Jagrati; Goel, Nidhi

doi:10.1109/icstm.2015.7225449

Cited by 7 publications

(3 citation statements)

References 5 publications

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“…Moreover, giving every master an equal share of the bus is not always a good idea. Because highly bus access masters will get scheduled as the idle masters [4,7,16].…”

Section: A Round Robinmentioning

confidence: 99%

“…Thus, scheduling mechanisms or "arbitration schemes", which are employed to synchronize and schedule the bus requesting from different bus masters in order to avoid contentions, have a major and important effect on the overall performance of the CMP design [3][4][5]. One of the challenges faced by the bus arbitration is to ensure that the sharing resources can be utilized and balanced distribution among the contention masters.…”

Section: Introductionmentioning

confidence: 99%

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A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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Abstract-Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to place several processors on the same chip die to get Chip Multiprocessor (CMP). The shared bus is the most common media used to connect these processors with each other and with the shared resources. Distributing the shared bus among the contention processors represents a critical issue that affects overall performance of the CMP. Optimal utilization with fair distribution of the shared bus represents another challenge. This paper introduces a bus arbitration scheme, which is an AgeBased Lottery (ABL) Arbitration that combines the lottery and age-based algorithms to overcome the shared bus challenges. The results show that the developed bus arbitration scheme maximizes the bus utilization and improves the distribution by at least 13.5% with an acceptable latency time comparing to the traditional bus arbitration schemes.

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“…Moreover, giving every master an equal share of the bus is not always a good idea. Because highly bus access masters will get scheduled as the idle masters [4,7,16].…”

Section: A Round Robinmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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“…The former captures the user's interest, and the latter captures the channel switching behaviour of the user. Gupta (2015) [13] proposed a con gurable arbiter for n users. The author uses round-robin techniques for high-speed SoC design.…”

Section: Introductionmentioning

confidence: 99%

Reducing Buffering Delay Using Memory Arbitration Mechanism for IPTV Based Applications

Cammillus

Shanmugavel

2021

Preprint

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High-speed communication needs high data transfer capacity and low latency, which are the key parameters of high-speed communication. Converging different applications such as IPTV to high-speed networks requires high transmission capacity and low delay with good QoS. Delays related to IPTV are video buffering, synchronization, and switching delay that obstructs the client's excellent quality assistance. In an application like IPTV, the video signals are buffered (happened to be in near end routers), and they are recombined for the client when it is asserted. To achieve the above stated, memory banks are deployed in a set top box that is used to buffer the video signals that enter in, thereby reducing expected delay. Playback mechanism is also included along with the proposed model to accomplish a better outcome. Proposed RTL schematic design was simulated using Verilog, executed in Model Sim – Altera 10.1b (Quartus II 12.1 edition) and Cadence 5.

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