High-speed communication needs high data transfer capacity and low latency, which are the key parameters of high-speed communication. Converging different applications such as IPTV to high-speed networks requires high transmission capacity and low delay with good QoS. Delays related to IPTV are video buffering, synchronization, and switching delay that obstructs the client's excellent quality assistance. In an application like IPTV, the video signals are buffered (happened to be in near end routers), and they are recombined for the client when it is asserted. To achieve the above stated, memory banks are deployed in a set top box that is used to buffer the video signals that enter in, thereby reducing expected delay. Playback mechanism is also included along with the proposed model to accomplish a better outcome. Proposed RTL schematic design was simulated using Verilog, executed in Model Sim – Altera 10.1b (Quartus II 12.1 edition) and Cadence 5.
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