Efficient approaches for designing reversible Binary Coded Decimal adders

Biswas, Ashis Kumer; Hasan, Md. Mahmudul; Chowdhury, Ahsan Raja; Babu, Hafiz Md. Hasan

doi:10.1016/j.mejo.2008.04.003

Cited by 115 publications

(50 citation statements)

References 15 publications

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“…15. [16][17][18][19]. It is observed that the proposed Pere gate fulfills its functionality while achieving much better results in terms of cell count, latency, cell area and latency and is hence an optimized design for further applications.…”

Section: G Ex-nor Gatementioning

confidence: 92%

“…clock zone 0 is represented by green, clock zone 1 by magenta, clock zone 2 by blue and clock zone 3 by white. Designing new reversible gates and circuits has always been a focus for researchers since the field of reversible computing has made its way into the design of architectures [17][18][19][20][21][22][23]. The design of these gates in QCA has been a more recent trend in order to investigate QCA as a breakthrough for the realization of such gates.…”

Section: Qca Architecturementioning

confidence: 99%

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Optimal Realization of Universality of Peres Gate Using Explicit Interaction of Cells in Quantum Dot Cellular Automata Nanotechnology

Bilal¹,

Ahmed²,

Kakkar³

2017

IJISA

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Abstract-The essence of the technology business lies in the improvements and advancements that are continuously taking place in the industry. From vacuum tubes, diodes and transistors to the concepts of nano level designing have by and large created a revolution in the history of mankind. The biggest milestone in this journey has been the CMOS technology which has managed to survive for decades and is still an ongoing research area. However, advancing the technology includes many other dimensions which need to be taken care of. As the devices go on decreasing in size with the improving technology the power dissipation in them becomes a major issue. To counter this, a new logic called reversible logic has come into the pool of research. Further a shift from the transistor based paradigm is being explored to go down to ultra-small structures. A major breakthrough in this can be the Quantum Dot Cellular Automata (QCA) Nanotechnology. In this paper we have given a review about how the reversible logic and QCA nanotechnology together result in ultra-low power designs. Further we have optimized the design of Peres reversible gate using the concepts of explicit interaction of cells in QCA and verified the universal functionality using the optimized designs.

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Section: G Ex-nor Gatementioning

confidence: 92%

Section: Qca Architecturementioning

confidence: 99%

Optimal Realization of Universality of Peres Gate Using Explicit Interaction of Cells in Quantum Dot Cellular Automata Nanotechnology

Bilal¹,

Ahmed²,

Kakkar³

2017

IJISA

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“…Modified TSG (MTSG) gate is a 4×4 reversible gate (Biswas et al, 2008a) with following input and output vectors, I v = (A, B, C, D) and O v = (P = A, Q = A⊕B, R = A⊕B⊕C and S = (A⊕B). C⊕ (AB⊕D).…”

Section: Reversible Mtsg Gatementioning

confidence: 99%

“…But in this circuit Peres gate is preferred because of lower quantum cost when compared to Toffoli gate (Biswas et al, 2008a). The combined AND-OR function i.e., C out = ZC in + C 4 is done by the fredkin gate.…”

Section: Proposed Reversible Carry Skip Addermentioning

confidence: 99%

Design of Optimal Carry Skip Adder and Carry Skip BCD Adder Using Reversible Logic Gates

Murugesan¹

2014

Journal of Computer Science

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Reversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate count, garbage outputs and constant inputs. This design forms the basis for different quantum ALU and embedded processors.

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“…Total number of reversible gates used in a circuit isconsidered to be as gate count (GA) [13]. Figure 2 shows that the required number of Peres gates (PG) for implementing a reversible full adder circuit is 2 (i.e GA=2).…”

Section: Gate Count(ga)mentioning

confidence: 99%