Efficient analog circuit synthesis with simultaneous yield and robustness optimization

Debyser, G.; Gielen, Georges

doi:10.1145/288548.288630

Cited by 38 publications

(32 citation statements)

References 10 publications

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“…The independence assumption in (8)- (11) simply implies that we do not know the correlation information between the late-stage coefficients {α L,n ; n = 1, 2, …, N} as a prior. However, the correlation between {α L,n ; n = 1, 2, …, N} will be taken into account by our proposed BMF algorithm through two different avenues: (i) when we legalize the prior distribution in (8) to guarantee that pdf L (g) in (2) is a valid probability density function, and (ii) when we calculate the posterior distribution of {α L,n ; n = 1, 2, …, N} once the late-stage simulation samples are available. In what follows, we will discuss these two topics (i.e., prior distribution legalization and posterior distribution calculation) in Section 3.2 and 3.3 respectively.…”

Section: Prior Knowledge Definitionmentioning

confidence: 99%

“…Remember that the prior distribution in (8) assumes that all coefficients {α L,n ; n = 1, 2, …, N} are mutually independent and each coefficient follows a Gaussian distribution. Since these Gaussian distributions associated with {α L,n ; n = 1, 2, …, N} are not bounded, our definition of prior distribution in (8) allows a coefficient α L,n to take any value ranging from −∞ to +∞.…”

Section: Prior Distribution Legalizationmentioning

confidence: 99%

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Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Zhang

Wang

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Parametric yield estimation is one of the most critical-yetchallenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75× runtime speedup over the traditional kernel estimation method.

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Section: Prior Knowledge Definitionmentioning

confidence: 99%

Section: Prior Distribution Legalizationmentioning

confidence: 99%

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Zhang

Wang

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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“…, n x . (Note that, in general, we can verify if this assumption holds since in many circuit designs it is easy to determine reasonable range of values for each design variable, e.g., (18).) We also assume that p i − 3σ p i > 0, i = 1, .…”

Section: B) Variance-not-linked-to-mean Variations In Design Variablementioning

confidence: 99%

“…Either lower bound (for maximal inscribed ellipsoid) or upper bound (for minimal circumscribed ellipsoid) of the actual parametric yield is estimated using this approach. The worst-case optimization techniques optimize worst-case circuit performances over all process and environmental variations (see, e.g., [16], [18]). Traditional worst-case optimization uses the process parameters taking values within a certain range which forms a tolerance "box," and the circuit performance is optimized for all of the "corners," or the vertices of the formed polyhedron.…”

mentioning

confidence: 99%

Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty

Hsiung

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full-custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metal-mask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and application-specific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metal-mask configurability, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound.

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“…Recently numerous papers (e.g. [12], [18]- [23]) are addressing the sizing problem from different aspects like process and operating tolerances, mismatch, yield and robustness.…”

Section: Introductionmentioning

confidence: 99%

Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points

Puhan

Bűrmen

Tuma

2003

Can. J. Electr. Comput. Eng.

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Circuit sizing (e.g. determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs started from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show, that from the cost function's point of view surprisingly many equivalent solutions exists.Proportinner les circuits, c'està dire, détérminer la largeur et la longueur des cannaux MOSFET, qui résultent en le circuit le plus approprié et le plus robuste, est sans doute un procès d'optimisation. Mais, le procès terminé, il y reste toujours une dilèmme, s'il on y existe pas une solutions meilleure. Si on prend les points du départ différents, on peut arriver aux minima locaux très divers. L'article propose de mettre en oeuvre un procès heuristique, en train duquel on fait marcher l'optimisation plusieures fois déterminant les points du départ très différents. Pendant chaque marche d'optimisation on essaie de trouver un minimum local d'une fonction de critère et ainsi obtenir des informations supplémentaires sur le circuit. L'article engage le fond mathématique de l'argorithme utilisé. Enfin, l'argorithme heuristique est mis sous l'épreuve en cadre des dessins réels intégrés d'amplificateur opérant. Le résultat est surprénant; du point du vu de la fonction de critère, il y existe beaucoup des solutionséquivalentes.

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Efficient analog circuit synthesis with simultaneous yield and robustness optimization

Abstract: Abstract

Cited by 38 publications

References 10 publications

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty

Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points

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