Efficiency of three‐level neutral‐point clamped converters: analysis and experimental validation of power losses, thermal modelling and lifetime prediction

Summary A new soft switching three‐level converter with two DC/DC circuits in the primary side and current double rectifiers in the secondary side is presented to realize the zero‐voltage switching operation, reduce the transformer secondary winding turns and the output current ripple, and lessen the voltage rating of rectifier diodes. Two DC/DC pulse‐width modulation circuits sharing same power switches with interleaved half switching cycle are adopted in the proposed converter to reduce the current rating of transformer primary windings. Two inductors and four diodes are adopted in the secondary side to achieve current double rectifier, reduce output ripple current, and decrease the transformer secondary winding turns. Based on the pulse‐width modulation scheme, the power switchers can be turned on at zero‐voltage switching operation. Laboratory experiments with a 1.44 kW prototype are provided to verify the theoretical analysis. Copyright © 2016 John Wiley & Sons, Ltd.

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“…The inductor voltages v Lo1 = v Lo2 = ÀV o such that i Lo1 and i Lo2 decrease. The diode currents i D1i D4 are expressed in (3)(4)(5)(6).…”

Section: Operation Principlementioning

confidence: 99%

Soft switching DC/DC converter with high voltage gain and less current ripple

Lin

Chen

2016

Circuit Theory & Apps

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“…. The electrical loading on switching devices results in power losses, which is the main cause of thermal overheating, thereby affecting the junction temperature T j of the device . The Thevenin equivalent thermal impedance between the junction and the heat sink Z th(j–h) is calculated as follows:

Z_{th (j–h)} = {falsefalse}_{\sum}^{i = 1} R_{i} (1 - e^{- \frac{t}{τ}})

…”

Section: Thermal Analysis Of Multilevel Invertersmentioning

confidence: 99%

An overheating‐tolerant space vector modulation algorithm for multilevel inverters

Aly

Dousoky

Shoyama

2016

IEEJ Transactions Elec Engng

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As promising and suitable candidates for high-power applications, multilevel inverters have become one of the most promising solutions in various applications. However, power switching devices are highly subjected to thermal overheating, which leads to shortened lifetime and reduced reliability. Thermal overheating may result from the degradation of power switching devices due to continuous overloading and power cycling. In addition, degradation and faults in the cooling system of power switching devices may cause thermal stresses as well. A new overheating-tolerant space vector modulation algorithm is proposed in this paper to alleviate thermal stresses from overheated power switching device. The proposed algorithm relies on using the redundancy property between switching states in multilevel inverters to continuously evaluate a cost function of the junction temperature of the overheated device for all possible switching sequence sets and then selects the optimal switching sequence. In addition, the proposed algorithm preserves the DC-link capacitor voltage without reduction in the output current of the inverter. The proposed algorithm is general, which can be applied to n-level inverters. Both simulation and experimental results reveal the efficient performance of the proposed algorithm using a three-level T-type inverter as a case study. Accordingly, the lifetime and reliability of the inverter are enhanced considerably using the proposed algorithm.

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“…Existing lifetime models to evaluate the effect of stress cycles are in general of two types: (i) analytical behavior models such as the Coffin-Manson [13], Coffin-Manson-Arrhenius, [14,15], Norris-Landzberg [16,17], and Bayerer [18,19] models, and (ii) physics-of-failure (PoF) models [8,20]. Previous studies of lifetime model were mainly focused at the device level under constant temperature cycling tests [8,21], and effect of accumulated fatigue was not considered and lifetime was accounted for by the loading amplitude alone.…”

Section: Introductionmentioning

confidence: 99%

Study on lifetime prediction considering fatigue accumulative effect for die‐attach solder layer in an IGBT module

Lai

Chen

et al. 2018

IEEJ Transactions Elec Engng

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An accurate lifetime model is needed in power electronic systems as a cost-effective means of improving reliability and performance assessment, which have long been highly desired to reduce the maintenance cost and to make the product more competitive in the market. Die-attach solder layer fatigue has been identified as one of the root causes of failure of power electronic modules. This paper presents "physics-of-failure lifetime model", which takes fatigue accumulative effect into consideration and can quantify the effect of long-term small-temperature cycling to device fatigue life cycle to estimate the lifetime of the power module. First, small T j power cycling tests were designed to obtain the effects of T j on aged and un-aged modules. They indicated that the traditional lifetime models were not accurate in predicting the lifetime of power modules. Therefore, a new time-domain crack propagation model based on the cumulative damage in the die-attach solder layer is proposed, which includes time-dependent material properties and temperature profiles. Moreover, power cycling experiments and simulations are conducted to demonstrate the method by comparing the number of cycles to failure.

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Efficiency of three‐level neutral‐point clamped converters: analysis and experimental validation of power losses, thermal modelling and lifetime prediction

Cited by 64 publications

References 12 publications

Soft switching DC/DC converter with high voltage gain and less current ripple

Soft switching DC/DC converter with high voltage gain and less current ripple

An overheating‐tolerant space vector modulation algorithm for multilevel inverters

Study on lifetime prediction considering fatigue accumulative effect for die‐attach solder layer in an IGBT module

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