Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair

DOI: 10.1109/aspdac.1995.486391

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Efficiency comparison of signature monitoring schemes for FSMs

Régis Leveugle²,

Abstract: ISBN: 4930813670This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented

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Cited by 5 publications

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Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

et al.

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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ISBN: 0818681683We present here the first version of an automatic tool for the synthesis of dataparts with fault detection or tolerance characteristics. This work is to be combined with solutions already proposed for controllers, in order to provide a complete control-dominated synthesis flow allowing the synthesis of control/data architectures with fault detection or tolerance capabilities

Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

et al.

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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ISBN: 0818681683We present here the first version of an automatic tool for the synthesis of dataparts with fault detection or tolerance characteristics. This work is to be combined with solutions already proposed for controllers, in order to provide a complete control-dominated synthesis flow allowing the synthesis of control/data architectures with fault detection or tolerance capabilities

Finite state machine synthesis with concurrent error detection

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³

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)

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A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are checked independently. By checking parity on the present state instead of the next state, this technique allows detection of errors in bistable elements (that were hitherto not detected by many previous techniques) while requiring no changes in the original machine specifications. This paper also examines design choices with respect to parity prediction circuits. Two such examined choices are the multi-parity-group and the single-paritygroup techniques. A new state encoding technique based on the JEDI program is developed for the synthesis of the next-state logic with an additional parity output. Synthesis results produced by our proposed procedure for the MCNC'89 FSM benchmark circuits show on average a 25% reduction in literal counts compared to previous techniques.

Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Proceedings of 14th VLSI Test Symposium

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ISBN: 0818673044This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow

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