ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow
ISBN: 0818681683We present here the first version of an automatic tool for the synthesis of dataparts with fault detection or tolerance characteristics. This work is to be combined with solutions already proposed for controllers, in order to provide a complete control-dominated synthesis flow allowing the synthesis of control/data architectures with fault detection or tolerance capabilities
ISBN: 0818673044This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow
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