Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

Lin, Chiung–Wei; Khan, Asif Islam; Salahuddin, Sayeef; Hu, Chenming

doi:10.1109/ted.2016.2514783

Cited by 174 publications

(70 citation statements)

References 13 publications

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“…In this condition, NCFETs become unstable, resulting in the hysteresis behavior [17]. Such a trade-off between high performance and hysteresis agrees well with previous results [12] [17]. Since hysteresis behavior is not desirable, we consider only hysteresis-free NCFETs hereafter.…”

Section: Characteristics Of Ncfetsupporting

confidence: 86%

See 1 more Smart Citation

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Seo

Lee

Shin

2017

IEEE Trans. Electron Devices

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Abstract-We investigate the performance of hysteresisfree short-channel negative-capacitance field-effect transistors (NCFETs) by combining quantum mechanical calculations with the Landau-Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of draininduced barrier lowering (DIBL) is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance (NDR) in the output characteristics of NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresisfree NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.Index Terms-Subthreshold swing, ferroelectric, negative capacitance FET, hysteresis behavior, drain-induced barrier lowering, Schmitt trigger inverter

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Section: Characteristics Of Ncfetsupporting

confidence: 86%

“…Kobayashi et al [11] suggested exploiting the ferroelectric properties to design low-power NCFETs. The dependences of NCFET performances on ferroelectric thickness (T F E ) have been studied extensively [12]- [16]. Khan et al [17] provided guidelines for parameters to develop low-power NCFETs.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Seo

Lee

Shin

2017

IEEE Trans. Electron Devices

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“…The specific application or device also needs to be considered, because it determines the environment of the ferroelectric and its response. FETs are currently the most interesting and beststudied case, and the impact of various design variables (size, shape, response and conductivity of the different components) on the volt age amplification effect is being intensively investigated, including by dynamic simulation studies 20,51,71,93,94,[108][109][110][111][112][113][114][115][116][117][118] . Applying NC effects in transistors is challenging owing to the presence of free carriers in the channel, which is in contact with the source and drain, complicating the realization of chargecontrol conditions as well as the stabilization of the NC state.…”

Section: Perspectivesmentioning

confidence: 99%

Ferroelectric negative capacitance

Íñiguez¹,

Zubko²,

et al. 2019

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, which needs to be positive owing to thermodynamic stability. However, this relation is also true if one of the local effective capacitances, for example, C 1 , is negative, as long as the condition C ≥ 0 is fulfilled. In this scenario, the application of an external voltage V results in V int = V(1 + C 2 /C 1) −1 at the interface between the two dielectrics, such that V int /V > 1 if C 1 < 0. That is, NC of one part of the system enables amplification of the voltage at the interface (fig. 1b). Contrary to the usual decrease in the overall capacitance when a regular (positive) capacitance is added in series, the addition of

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“…[42,46] Nevertheless, the disadvantage of MFMIS gate structure is that the gate leakage cannot be avoided in practical devices. [100,101] [41] To reduce the negative effects of the gate leakage, Khan et al proposed a work-function engineering method to maintain steep SS and high I D by the appropriate choice of the intermediate metal layer.…”

Section: Simulationmentioning

confidence: 99%

Ferroelectric Negative Capacitance Field Effect Transistor

Wang

et al. 2018

Adv Elect Materials

115

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such as steep subthreshold swing (SS), high switching ratio (I on /I off ), adjustable hysteresis, compatibility with standard semiconductor fabrication processes, and environmental friendliness, promotes NCFET to be a promising candidate to lower power consumption and solve the heat problem in ULSI.As early as the 1960s, the concept of negative capacitance (NC) was proposed in amorphous semiconductor chalcogenides thin film, [25,26] then the NC effect was observed in several devices, such as p-n junctions, [27,28] Schottky diodes, [29,30] metal-insulator-metal diodes, [31] and others. [32][33][34][35] Concretely, the NC effect occurs when the reciprocal of the second derivation of potential energy U with respect to the ferroelectric polarization charge Q F is negative, which is usually achieved during the switching process of ferroelectric polarization. [36,37] NCFET achieves steep SS through the NC voltage amplification effect by adding a ferroelectric layer into the transistor gate stack. [22] NCFET simulation methods vary according to the types of transistor gate structures-metal ferroelectric semiconductor field-effect transistor (MFSFET), metal ferroelectric insulator semiconductor field-effect transistor (MFISFET), and metal ferroelectric metal insulator semiconductor field-effect transistor (MFMISFET). However, the basic principle is to realize a match between the channel charge Q and the ferroelectric polarization charge P, [38][39][40][41][42] no matter what the specific gate structure is.Furthermore, the influencing factors of NCFET's electrical properties have been qualitatively analyzed and summarized according to numerous simulation results. Commonly, a tradeoff exists between SS and hysteresis, [22] and we can design and manipulate the gate structure, [41] ferroelectric thickness (t Fe ), [22] ferroelectric material parameters, [38] silicon doping concentration, [39,43] temperature, [44] work frequency, [45][46][47][48] and high-κ dielectric [23,49,50] to optimize the electrical performance of NCFET and meet specific practical application requirement.The experimental researches on NCFETs can be mainly classified into three categories based on various kinds of ferroelectrics. First, the NCFET based on organic ferroelectric-poly(vinylidene difluoride-trifluoroethylene)[P(VDF-TrFE)], has been experimentally demonstrated, and achieves minimum SS (SS min ) = 13 mV dec −1 with small hysteresis. [51,52] Second, the NCFET based on lead zirconate titanate (PZT), a type of inorganic perovskite-type ferroelectric, exhibits hysteretic switching with With the progress in silicon circuit miniaturization, lowering power consumption becomes the major objective. Supply voltage scaling in ultralargescale integration (ULSI) is limited by the physical barrier termed "Boltzmann Tyranny." Moreover, considerable heat is inevitably generated from the ultrahighly integrated circuit. To solve these problems, a ferroelectric negative capacitance field-effect transistor (Fe-NCFET) is proposed in order to reduce the subthresho...

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Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

Cited by 174 publications

References 13 publications

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Ferroelectric negative capacitance

Ferroelectric Negative Capacitance Field Effect Transistor

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