Effects of the Deposition Sequence on Amorphous Silicon Thin-Film Transistors

Hiranaka, Kouichi; Yoshimura, Tetsuzo; Yamaguchi, T.

doi:10.1143/jjap.28.2197

Cited by 37 publications

(8 citation statements)

References 7 publications

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“…7 The stress at the SiNJa-Si:H interface is stronger than those in bulk adjacent films. This high stress could In a TFT when the width of the tail state density in the a-Si:H layer increases, its field effect mobility decreases and the subthreshold slope increases] ~8 Since all TFTs in this paper have the same a-Si:H layer, the mobility is mainly influenced by the interface characteristics.…”

Section: Resul Ts and Discussionmentioning

confidence: 99%

Thin Film Transistors with Graded SiN x Gate Dielectrics

Kuo

1994

J. Electrochem. Soc.

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This paper presents results on thin film transistors with graded SiN~ gate dielectrics. All SiN= and a-Si:H films were prepared using 250~ plasma-enhanced chemical vapor deposition processes. Device characteristics such as mobility, threshold voltage, subthreshold slope, and on/off current are discussed. The graded gate dielectric thin film transistor (TFT) may have better or worse device performance compared with the single gate dielectric TFT, depending on the interface dielectric deposition condition. The interface SiN= deposition process influences the intensity density of states between the a-Si:H layer and the gate SiN~ layer as well as the states between the first and the second (interface) SiN= layers. The stress mismatch between the first and the second SiN= layers also has a profound influence on TFT characteristics. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 134.129.182.74 Downloaded on 2015-06-05 to IP

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Section: Resul Ts and Discussionmentioning

confidence: 99%

Thin Film Transistors with Graded SiN x Gate Dielectrics

Kuo

1994

J. Electrochem. Soc.

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“…The device structure adopted in this paper is an amorphous silicon based inverted-staggered bottom gate phototransistor. The invertedstaggered bottom gate structure has better characteristics than the top gate (normal or staggered) one [20], [21]. Compared with the normal, staggered transistor, the inverted, staggered TFT has higher field effect mobility µeff , lower threshold voltage Vth, higher on-current Ion and lower threshold shift ∆Vth under stress [20], [21].…”

Section: Device Structurementioning

confidence: 99%

An Amorphous Silicon Photo TFT with Si3N4/Al2O3 or HfO2 Double Layered Insulator for Digital Imaging Applications

Siham¹,

Hafdi²

2019

J. Microw. Optoelectron. Electromagn. Appl.

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This paper focuses on amorphous silicon photo thin-film transistors with double layered insulator using Si3N4/Al2O3 or HfO2 as candidates for the succession of Si3N4 as a traditional insulator in the fabrication of hydrogenated amorphous silicon thin-film transistors. Whether for industry or for research, there is a need to investigate the use of thin gate insulators for these devices to overcome leakage current. Our investigations included direct and transfer characteristics in dark and under illumination, generated photocurrents, external quantum efficiency and responsivity. Performance is evaluated in terms of the dielectric thickness and nature. Improvements in the proposed structures regarding off-current, responsivity and quantum efficiency are achieved via these materials. Comparing with Si3N4/HfO2 transistor, the Si3N4/Al2O3 device shows the lowest off-current. The HfO2 device presents the highest oncurrent when illuminated. The generated photocurrent is higher for Si3N4/HfO2 transistor revealing a lower amount of trapped charge. Under illumination and for very thin thicknesses, both devices enhance the Si3N4 device off-current and reach Si3N4 single layer dielectric based phototransistor performance. external quantum efficiency and responsivity are higher in HfO2 devices comparing with Al2O3 devices. The results are promising and may support further investigations in order to develop high k gate insulators for MIS photo thin-film transistors.

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“…The µ fe of the TFTs on the SS substrate showed a lower value than that of the TFTs on the glass substrate, due to the localized state distribution in the a-Si:H film. 6 The increments in the width of the tail states cause a decrease in µ fe . There have been some reports that a lower activation energy E a is the result of a narrower tailstate distribution.…”

Section: Electrical Characteristics Of A-si:h Tftsmentioning

confidence: 99%

“…An increase in the width of the tail states occurred with a decrease in µ fe . 6 We also measured the source-drain-current activation energy versus gate voltage (V ds = 15 V) for thermal-annealed a-Si:H TFTs. The minimum activation energy, approached at the highest gate voltage (30 V), was a measure of the tail-state distribution and had values of 78, 89, and 105 meV for the a-Si:H TFTs annealed at 150, 200, and 230°C as shown in Fig.…”

Section: Electrical Stability Of A-si:h Tftsmentioning

confidence: 99%

Effects of post‐annealing on a‐Si:H TFT characteristics fabricated on stainless‐steel substrate

Han¹,

Kim²,

Chung³

2007

J Soc Info Display

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Abstract— A 14.1‐in.‐diagonal backplane employing hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) was fabricated on a flexible stainless‐steel substrate. The TFTs exhibited a field‐effect mobility of 0.54 cm2/V‐sec, a threshold voltage of 1.0 V, and an off‐current of 10−13 A. Most of the electrical characteristics were comparable to those of the TFTs fabricated on glass substrates. To increase the stability of a‐Si:H TFTs fabricated on stainless‐steel substrate, the specimens were thermally annealed at 230°C. The field‐effect mobility was reduced to 71% of the initial value because of the strain of the released hydrogen atoms and residual compressive stress in a‐Si:H TFT under thermal annealing at 230°C.

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Effects of the Deposition Sequence on Amorphous Silicon Thin-Film Transistors

Cited by 37 publications

References 7 publications

Thin Film Transistors with Graded SiN x Gate Dielectrics

Thin Film Transistors with Graded SiN x Gate Dielectrics

An Amorphous Silicon Photo TFT with Si3N4/Al2O3 or HfO2 Double Layered Insulator for Digital Imaging Applications

Effects of post‐annealing on a‐Si:H TFT characteristics fabricated on stainless‐steel substrate

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