Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures

Kim, Jungsik; Lee, Junyoung; Rim, Taiuk; Baek, Chang‐Ki; Lee, Jeong-Soo

doi:10.1016/j.mee.2015.09.018

Cited by 10 publications

(7 citation statements)

References 9 publications

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“…Although the latter seems to be gaining traction in recent literature, a definitive conclusion has not been reached, yet, and a recent study of the different dependences implied by such models can be found in [88,89]. The above-mentioned numerical models of conduction have been used to investigate the effect of GBs on variability in nanowires [90][91][92][93][94][95] and 3D NAND devices [96,97]. A recent study based on a drift-diffusion transport within the grains and thermionic emission at the GBs [98][99][100][101] has demonstrated a good capability to reproduce several features of experimental data, including its temperature dependence.…”

Section: Polysilicon Conductionmentioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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Section: Polysilicon Conductionmentioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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“…1(b). 23,24) The V th variation of the target cell (WL1) due to various SGB positions was extracted after the programming of the target cell. The trap density of charge-trapping nitride layer (N NIT ) was 2.2 × 10 19 cm −3 [see the nitride layer in a Fig.…”

Section: Simulation Structure and Bias Conditionsmentioning

confidence: 99%

“…Channel doping concentration N A (cm −3 ) 1 0 16 S=D doping concentration N D (cm −3 ) 1 0 20 Grain boundary trap states N GB 23,24) (cm −2 eV −1 ) 1 0 12 -10 14 energy levels of electrons and holes were assumed to be 1.2 and 2.5 eV, respectively. 25,26) The program bias condition was a 16 V single pulse with a 1 ms hold time, and the read bias increased up to 4 V at various V d values.…”

Section: Simulation Structure and Bias Conditionsmentioning

confidence: 99%

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Kim

Baek

Lee

2018

Jpn. J. Appl. Phys.

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The effects of single grain boundary (SGB) position and stored electron charges in an adjacent cell in silicon-oxide-nitride-oxide-silicon (SONOS) structures on the variations of threshold voltage (V th ) were investigated using technology computer-aided design (TCAD) simulation. As the bit line voltage increases, the SGB position causing the maximum V th variation was shifted from the center to the source side in the channel, owing to the drain-induced grain barrier lowering effect. When the SGB is located in the spacer region, the potential interaction from both the SGB and the stored electron charges in the adjacent cell becomes significant and thus resulting in larger V th variation. In contrast, when the SGB is located at the center of the channel, the peak position of potential barrier is shifted to the center, so that the influence of the adjacent cell is diminished. As the gate length is scaled down to 20 nm, the influence of stored charges in adjacent cells becomes significant, resulting in larger V th variations.

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“…Charge transport is actually limited by the energy barriers at the grain boundaries (due to the trapped charge) rather than by transport within the grains, except for very large grain size [339]. Several works have exploited numerical simulations to investigate the effect of grain boundaries on variability in nanowires [340][341][342][343][344][345] and 3D NAND devices [346,347]. However, several important features of such models still have to be assessed, such as the grain size [348,349], the density and energy distribution of grain boundary traps [350,351], and the mobility degradation and conduction process at the grain boundaries [352,353].…”

Section: Polysilicon Grainsmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures

Cited by 10 publications

References 9 publications

Random Telegraph Noise in 3D NAND Flash Memories

Random Telegraph Noise in 3D NAND Flash Memories

Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon–oxide–nitride–oxide–silicon NAND flash memory

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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