2011
DOI: 10.1149/1.3529237
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Effects of Selective and Nonselective Wet Gate Recess on InAlAs∕InGaAs Metamorphic Field-Effect Transistors with Double Delta Doping in InGaAs Channels

Abstract: This investigation reports on the first symmetrically double-delta-doped channel InAlAs/InGaAs/GaAs metamorphic field-effect transistor ͑MFET͒. Two types of devices are fabricated as follows. In the fabrication of the first, the gate recessing steps are carried out using nonselective etching solution ͑phosphoric acid/hydrogen peroxide mixtures͒. In the fabrication of the second, a pH 5.5 selective succinic acid:ammonia hydrogen peroxide:water wet chemical etching liquid is adopted to form the gate recess. A su… Show more

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Cited by 10 publications
(6 citation statements)
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“…In order to accommodate the lattice-mismatch-induced defects between the top GaAs 0.45 Sb 0.55 layer and the Si substrate, a two-step-graded GaAsSb buffer layer with different Sb compositions was incorporated. Superior device (quantum well transistors, FETs, tunnel diodes, and TFETs) 1,[19][20][21][22][23][24][25] performances were achieved when the surface rms roughness was similar to or higher than the results reported in this work. Therefore, one can achieve excellent metamorphic device performance on this virtual substrate.…”
supporting
confidence: 79%
See 1 more Smart Citation
“…In order to accommodate the lattice-mismatch-induced defects between the top GaAs 0.45 Sb 0.55 layer and the Si substrate, a two-step-graded GaAsSb buffer layer with different Sb compositions was incorporated. Superior device (quantum well transistors, FETs, tunnel diodes, and TFETs) 1,[19][20][21][22][23][24][25] performances were achieved when the surface rms roughness was similar to or higher than the results reported in this work. Therefore, one can achieve excellent metamorphic device performance on this virtual substrate.…”
supporting
confidence: 79%
“…These surface roughness values are rather high, although they are comparable to the reported results for metamorphic graded buffers with lattice mismatch in the range from 4 to 8%. 1,[19][20][21][22][23][24][25] In this study, the lattice mismatch of the uppermost GaAs 0.45 Sb 0.55 layer is >12% with respect to the Si substrate, and the lattice-mismatch-induced surface roughness cannot be avoided for metamorphic growth. However, the defect control within the buffer and the uppermost GaAs 0.45 Sb 0.55 layer of interest is an important design criterion for a lattice-mismatch system and can severely impact the device performance.…”
mentioning
confidence: 87%
“…In particular, high electron mobility transistors (HEMTs) based on the AlGaAs/GaAs material system had paid attention to high-speed digital and high-frequency microwave circuits, due to the extremely high mobility of two-dimensional electron gas (2-DEG) accumulating at the heterojunction. 1,2 Thus, the carriers in the channel could improve the output current and high frequency characteristic. However, due to the presence of 2DEG at heterojunction, the depletion-mode (D-mode) operation brings about undesired harassment on devices and circuits, such as extra-power dissipation at idle operated time.…”
mentioning
confidence: 99%
“…Recently, there has been considerable interest in the potential of III-V GaAs-based field-effect transistors (FETs) in signal amplifier and advanced logic applications. 1,2 In order to promote the performance, the GaAs channel layer could be replaced with an InGaAs strain layer because the InGaAs strain channel layer has smaller electron effective mass, higher electron mobility, and higher peak electron velocity, [3][4][5] though the In mole fraction as well as the thickness of InGaAs strain layer is critically limited. 6 Another heterostructure, i.e., In 0.5 (Ga 1-x Al x ) 0.5 P/GaAs, has attracted researcher's attention for the high-speed device and circuit applications.…”
mentioning
confidence: 99%