2020
DOI: 10.1109/ted.2020.2990135
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Effects of Redundant Electrode Width on Stability of a-InGaZnO Thin-Film Transistors Under Hot-Carrier Stress

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Cited by 10 publications
(7 citation statements)
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“…It is worth noting that, at the very beginning of the sensing measurement of, for example, the 90:9:1 ITWO transistor in Figure 3b, the drain current slightly decreases with time, which should be due to the trapping process of majority carriers, i.e., electrons, at the ITWO/SiO 2 interface. 50 This phenomenon is an indicator of the existence of traps at the interface. Once all traps at the interface are filled after a period of time, the transistor presents a stable drain current.…”
Section: Proximity Sensing Of Itwo Transistor With Extended-gate Conf...mentioning
confidence: 99%
“…It is worth noting that, at the very beginning of the sensing measurement of, for example, the 90:9:1 ITWO transistor in Figure 3b, the drain current slightly decreases with time, which should be due to the trapping process of majority carriers, i.e., electrons, at the ITWO/SiO 2 interface. 50 This phenomenon is an indicator of the existence of traps at the interface. Once all traps at the interface are filled after a period of time, the transistor presents a stable drain current.…”
Section: Proximity Sensing Of Itwo Transistor With Extended-gate Conf...mentioning
confidence: 99%
“…It can be observed that TFT with larger channel width (W) shows larger ΔVth over time. For smaller size TFTs, the heating induced by current stressing is more difficult to be dissipated, and thus better PBS stability is able to be achieved [17][18][19]. Therefore, using smaller size TFTs, the proposed gate driver in array design is able to achieve better operation stability.…”
Section: Layout Placement For In-array Integrationmentioning
confidence: 99%
“…In order for oxide TFTs to replace the Si CMOS backplane, the facile integration process of submicron scale devices should be developed on the glass substrate. Furthermore, short‐channel effects such as drain‐induced barrier lowering (DIBL), hot carrier effects (HCE), and inappropriate leakage current are major concerns 17–19 . Non‐planar architectures such as three‐dimensional (3D)‐vertical, recess channel, or FinFET structures can provide solutions to these fundamental issues.…”
Section: Introductionmentioning
confidence: 99%