Effects of radiation and charge trapping on the reliability of high- κ gate dielectrics

Felix, J.A.; Schwank, J.R.; Fleetwood, D.M.; Shaneyfelt, M.R.; Gusev, Evgeni

doi:10.1016/j.microrel.2003.12.005

Cited by 103 publications

(70 citation statements)

References 85 publications

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“…Thus, no significant irradiation or stress induced interface trap buildup is observed in these devices [37], [38]. This is not unusual for [17], [21], [25], although significant interface-trap buildup has been observed in other types of devices processed differently [39], [40]. Electric fields were corrected for gate (TiN)-to-silicon work function; gate biases of 2 V/ 2 V for 7.5 nm devices correspond to values of 2.7 MV/cm and 2.0 MV/cm, and gate biases of 1 V/ 1 V for 3 nm devices are equivalent to values of 3 MV/cm and 1.9 MV/cm, respectively.…”

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confidence: 61%

“…While significant performance improvement was achieved recently [4], it is important to establish increased reliability in these materials and devices [5]- [9]. Significant reliability concerns include negative bias temperature instability (NBTI), time dependent dielectric breakdown (TDDB) [10], [11], carrier injection [12]- [16], and radiation induced charge trapping [17].…”

mentioning

confidence: 99%

“…Early work on and/or Hf silicate-based devices concentrated on studying the radiation response of thicker dielectrics, primarily using capacitors [17], [20], [21]. In an ionizing radiation environment, hole trapping is usually the dominant source of radiation-induced oxide-trap charge in -based devices, with some electron trapping possible at high radiation doses and/or for extreme electrical stressing conditions, due to low capture-cross section neutral electron traps in the oxides [22], [23].…”

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confidence: 99%

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Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

Dixit

Zhou

Schrimpf

et al. 2007

IEEE Trans. Nucl. Sci.

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Radiation induced charge trapping in ultrathinHfO 2 -based n-channel MOSFETs is characterized as a function of dielectric thickness and irradiation bias following exposure to 10 keV X-rays and/or constant voltage stress. Positive and negative oxide-trap charges are observed, depending on irradiation and bias stress conditions. No significant interface-trap buildup is found in these devices under these irradiation and stress conditions. Enhanced oxide-charge trapping occurs in some cases for simultaneous application of constant voltage stress and irradiation, relative to either type of stress applied separately. Room temperature annealing at positive bias after irradiation of transistors with thicker gate dielectric films leads to positive oxide-trapped charge annihilation and/or neutralization in these devices, and net electron trapping. The oxide thickness dependence of the radiation response confirms the extreme radiation tolerance of thin HfO 2 dielectric layers of relevance to device applications, and suggests that hole traps in the thicker layers are located in the bulk of the dielectric. A revised methodology is developed to estimate the net effective charge trapping efficiency, , for high-dielectric films. As a result, estimates of for Hf silicate capacitors and Al 2 O 3 transistors in previous work are reduced by up to 18%.Index Terms-Constant-voltage-stress (CVS), Hafnium oxide (HfO 2 ), high-, metal-oxide-semiconductor-field-effect-transistors (MOSFETs), radiation damage, recovery, ultrathin, X-ray.

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confidence: 61%

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confidence: 99%

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confidence: 99%

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Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

Dixit

Zhou

Schrimpf

et al. 2007

IEEE Trans. Nucl. Sci.

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“…Furthermore, the tunnel current will tend to fill trapped holes, repairing the damage caused by an ionizing event. The very thin Al 2 O 3 films used in MTJs have demonstrated very little damage from TID levels of above 10 kGy [120]. The degradation due to TID is small compared to temperature and manufacturing variation so it is likely that existing MTJ memory circuits will easily cope with TID effects.…”

Section: Radiation Effectsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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“…For example, previous work by Felix et al. [6], [8] focused on Hf silicates with no nitride processing, and Felix et al. [9] and Zhou et al.…”

Section: Introductionmentioning

confidence: 99%

Total Dose and Bias Temperature Stress Effects for HfSiON on Si MOS Capacitors

Chen

Mamouni

Zhou

et al. 2007

IEEE Trans. Nucl. Sci.

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We have performed an experimental study of the effects of ionizing radiation and bias-temperature stress on Si MOS devices with HfSiON gate dielectrics. We compare the responses of homogeneous high-Si 3 N 4 films and low-Si 3 N 4 films that contain crystalline HfO 2 . We observe that the low-Si 3 N 4 films are more sensitive to ionizing radiation than the high-Si 3 N 4 films. In particular, the low-Si 3 N 4 film that includes crystalline HfO 2 is especially vulnerable to electron trapping due to substrate injection under positive irradiation bias. Both film types exhibit reduced radiation-induced charge trapping relative to previous Hf silicates. The high-Si 3 N 4 film exhibits 16 less radiation-induced net oxide-trap charge density than earlier Hf silicate films processed without nitride. We also find that these devices are relatively robust against bias-temperature stress instabilities. Consistent with the radiation response, the low-Si 3 N 4 devices also display elevated levels of charge trapping relative to the high-Si 3 N 4 devices during bias-temperature stress.

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Effects of radiation and charge trapping on the reliability of high- κ gate dielectrics

Cited by 103 publications

References 85 publications

Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

Magnetic Random Access Memory for Embedded Computing

Total Dose and Bias Temperature Stress Effects for HfSiON on Si MOS Capacitors

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