Effects of operator grouping on the VLSI final test facility layout scale

We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an eventdriven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMs and SDRAMs are considered. The overall number of planned production chips during a month is 3 millions. The number ofchips simultaneously tested is 32,64, 128, and 256. Simulations for six months were canied out as a function of number of memory test system:. by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.

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“…In order to deal with this situation, the station data stmcture was formed for each machine group in our previous simulation analysis [1]- [6].…”

Section: Production Dispatching Rulesmentioning

confidence: 99%

“…We have already evaluated various items such as 0-7803-7673-0/03/$17.00 G2003 IEEE mm wafer and small lot size on the final test process through the simulation analysis [11- [6]. In the simulation, a combination of the discrete event simulation and detailed parametric models of the VISI manufacturing system is used.…”

Section: Introductionmentioning

confidence: 99%