Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET

Thingujam, Terirama; Son, Dae‐Ho; Kim, Jeong-Gil; Cristoloveanu, S.; Lee, Jung‐Hee

doi:10.1109/ted.2019.2963427

Cited by 20 publications

(13 citation statements)

References 22 publications

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“…This scattering mechanism occurs due to the high optical phonon of GaN [51] and the usage of Al2O3 as the gate dielectric. The use of this dielectric results in near-zero gate hysteresis, however the interface effect between this dielectric with GaN NW triggers phonon scattering [52]. Furthermore, we discuss the effect of diameter in 1 NW FET for = 9 V from the work of Fatahilah et al [11].…”

Section: Resultsmentioning

confidence: 98%

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

et al. 2021

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Section: Resultsmentioning

confidence: 98%

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

et al. 2021

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“…The channel and the source/drain access regions were doped with 5 × 10 17 cm −3 and 2 × 10 18 cm −3 , respectively. The dimensions of the MOSFETs considered in this work are based on the experimentally obtained devices [19] already fitted to simulation in [18], scaled down considering experimentally obtainable dimensions based on the present technology for GaN material.…”

Section: Structure and Simulation Modelmentioning

confidence: 99%

“…Vertical nanowire architectures are also reported to show excellent performances due to its structural advantages [15]- [17]. Recently, we have reported a successful fabrication of the GAA GaN vertical nanowire MOSFET for a possible logic application with top-down approach and already analysed the performances in details [18]- [20]. Studies on nanowire channels with different geometry, based on basic material parameters of GaN, have shown that MOSFET with triangular-shaped nanowire channel exhibits better performances [21], [22].…”

Section: Introductionmentioning

confidence: 99%

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

et al. 2021

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The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio (I ON /I OFF ) of ∼10 8 . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.

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“…The III-V semiconductors have been reported as potential alternative channel materials as they can overcome the scaling limit of traditional Si-based CMOS technology [20]- [22]. The III-V semiconductor is becoming a better choice for future transistor technology because of their superior performances, including extremely-low OFF-state leakage current, suppressed trapping effect, high-linearity characteristics, and excellent gate controllability [23]- [25]. Nonetheless, few reports are analyzing the performances of JLMOSFETs using III-V semiconductors as channel materials.…”

Section: Introductionmentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

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In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for highperformance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s * tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel's device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ∼0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.INDEX TERMS GaAs, GaSb, double gate, junctionless MOSFETs, nano-scaled device, short-channel effects (SCEs), high-performance switching.

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Effects of Interface Traps and Self-Heating on the Performance of GAA GaN Vertical Nanowire MOSFET

Cited by 20 publications

References 22 publications

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

Investigation of Electrical Behaviors Observed in Vertical GaN Nanowire Transistors Using Extended Landauer-Büttiker Formula

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

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