Effects of hot carriers in offset gated polysilicon thin-film transistors

Hatzopoulos, A.A.; Tassis, D. H.; Arpatzanis, N.; Dimitriadis, C. A.; Kamarinos, G.

doi:10.1016/j.microrel.2005.07.004

Cited by 4 publications

(2 citation statements)

References 17 publications

(24 reference statements)

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“…Unfortunately, this type of structure often leads to a device degradation by introducing a large series resistance in the source and drain regions. 10,11) As mentioned previously, the fabrication method employed in this study yields an offset TFT structure with a minimum offset length of about 0.5 mm. These offset regions introduce series resistance to the total resistance.…”

Section: Degradation Of the Short Channel Tft Performance Due To The ...mentioning

confidence: 96%

Investigation of Aluminum Metallized Source/Drain Thin Film Transistors Using a Self-Aligned Fabrication Process

Duy

Lee

Jung

et al. 2010

Jpn. J. Appl. Phys.

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We consider the polarization of unstable type-IIB D0-branes in the presence of a background five-form field strength. This phenomenon is studied from the point of view of the leading terms in the non-abelian Born Infeld action of the unstable D0-branes. The equations have SO(4) invariant solutions describing a non-commutative 3-sphere, which becomes a classical 3-sphere in the large-N limit. We discuss the interpretation of these solutions as spherical D3-branes. The tachyon plays a tantalizingly geometrical role in relating the fuzzy S 3 geometry to that of a fuzzy S 4 .

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Section: Degradation Of the Short Channel Tft Performance Due To The ...mentioning

confidence: 96%

Investigation of Aluminum Metallized Source/Drain Thin Film Transistors Using a Self-Aligned Fabrication Process

Duy

Lee

Jung

et al. 2010

Jpn. J. Appl. Phys.

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“…35) These results suggest that the oxide charge and the SiO 2 / c-Si interface dominate the degradation during positive gate bias stress. 36,37) Figure 12 shows the transfer characteristics of the TFTs with and without TPJ annealing, measured before and after applying the bias stress with the gate and drain biases of V g ¼ 1:7{3:0 V and V d ¼ 20 V at room temperature, which corresponds to the drain avalanche hot carrier (DAHC) generation condition. After the stress application, the on-state current reduced.…”

Section: Improvement Of Gate Sio 2 Film Qualitymentioning

confidence: 99%

Application of Thermal Plasma Jet Irradiation to Crystallization and Gate Insulator Improvement for High-Performance Thin-Film Transistor Fabrication

Higashi¹,

Hayashi²,

Hiroshige³

et al. 2011

Jpn. J. Appl. Phys.

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We study the charged Higgs effects on the decays of B − → τν τ and B → P (V ) ν with P = π + , D + and V = ρ + , D * + . We concentrate on the minimal supersymmetric standard model with nonholomorphic terms at a large tan β. To extract new physics contributions, we define several physical quantities related to the decay rate and angular distributions to reduce uncertainties from the QCD as well as the CKM elements. With the constraints from the recent measurement on the decay branching ratio of B − → τν τ , we find that the charged Higgs effects could be large and measurable.

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A novel fabrication process of a gate offset nonvolatile memory on glass and the influence of the gate offset structure on the device characteristics

Duy

Lakshminarayan²,

Jung

et al. 2011

Solid-State Electronics

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Effects of hot carriers in offset gated polysilicon thin-film transistors

Cited by 4 publications

References 17 publications

Investigation of Aluminum Metallized Source/Drain Thin Film Transistors Using a Self-Aligned Fabrication Process

Investigation of Aluminum Metallized Source/Drain Thin Film Transistors Using a Self-Aligned Fabrication Process

Application of Thermal Plasma Jet Irradiation to Crystallization and Gate Insulator Improvement for High-Performance Thin-Film Transistor Fabrication

A novel fabrication process of a gate offset nonvolatile memory on glass and the influence of the gate offset structure on the device characteristics

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