Effects of high-concentration phosphorus doping on crystal quality and lattice strain in SiGe HBTs

Oda, Katsuya; Miura, Makoto; Shimamoto, H.; Washio, Katsuyoshi

doi:10.1016/j.apsusc.2008.02.123

Cited by 4 publications

(1 citation statement)

References 14 publications

(12 reference statements)

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“…This roughness is consistent with previous observations and has been attributed to surface segregation of P atoms during growth. 7,8 Micro-scale roughness should not, however, affect the ability to fabricate ohmic contacts. Carrier concentrations in the Si and III-V films are critically important to ohmic contact formation.…”

Section: Discussionmentioning

confidence: 99%

Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Pacella

Mukherjee

Bulsara

et al. 2013

ECS J. Solid State Sci. Technol.

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Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/In x Ga 1-x As interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/In x Ga 1-x As yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/Al x Ga 1-x As laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices. Integration of III-V compound (III-V) semiconductors with Si complementary metal-oxide semiconductor (CMOS) has been an area of great interest because of the circuit performance enhancement that can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V device growth.1-3 CMOS devices are fabricated on the surface silicon and III-V devices are built on the template layer in windows. In collaboration with other groups, we have successfully demonstrated differential amplifiers with InP heterojunction bipolar transistors (HBT) and Si CMOS devices on SOLES substrates. 4 In this previous work, Si and III-V contact metallization steps were performed separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic integration.A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes exposure of III-V materials to the CMOS sequence will cause the least disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the growth process.Using CMOS-friendly metals and processing steps which parallel those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is low to minimize effects on the III-V devic...

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Section: Discussionmentioning

confidence: 99%