Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes

Narasimham,; Bhuva,; Schrimpf,; Massengill,; Gadlage,; Holman,; Witulski,; Robinson, William H.; Black,; Benedetto,

doi:10.1109/radecs.2007.5205574

Cited by 8 publications

(7 citation statements)

References 12 publications

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“…The final important item to point out about the design of the SET circuit is the layout of the Schmitt trigger inverters. Inverter-to-inverter spacing [10], PMOS-NMOS distance [11], and well contacting schemes [12] are all important factors in determining SET widths. In Fig.…”

Section: Design Of the Subthreshold Single-event Transient Characmentioning

confidence: 99%

Alpha-particle and neutron-induced single-event transient measurements in subthreshold circuits

Gadlage¹,

Roach²,

Duncan³

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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Experimental data from alpha particle, neutron, and heavy ion testing are discussed and analyzed from a subthreshold voltage SET characterization circuit. Using a Schmitt trigger inverter target chain fabricated in a 28-nm bulk CMOS process, SET pulse widths are captured from an operating voltage down to 0.32 V. These results show that energetic particles can induce SET pulse widths that range up to hundreds of nanoseconds when operating at voltages well below the nominal voltage. Additionally, the results show that sub-Vt circuits are significantly more susceptible, as compared to circuits operating at nominal voltages, to low-energy particles inducing SETs that have a high probability of being latched as errors in a combinatorial logic design.

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Section: Design Of the Subthreshold Single-event Transient Characmentioning

confidence: 99%

Alpha-particle and neutron-induced single-event transient measurements in subthreshold circuits

Gadlage¹,

Roach²,

Duncan³

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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“…Despite of the difference of gate shapes, the W /L of counterpart transistors and the size, number of substrate/well contacts as well as the distance between the contacts and the active areas are all the same in the two inverters. Guard ring is regarded as an effective approach to helps maintain the well potential, and prevents the parasitic bipolar transistor from turning on [3]. Simulations were carried on the (enclosed layout and standard layout with guard ring respectively.…”

Section: Simulation Setupmentioning

confidence: 99%

Impact of gate shapes on single event transients

Xing

Wang

Yue

2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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3D-TCAD simulations in a O.18um process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS. The results turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors. The mechanisms and process that affect the charge collection of different layout structures are studied. Ssuggestions are made towards design guidelines and hardening approaches.

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“…9. The most effective cases were found to be the introduction of a well contact stripe between PMOS devices increasing the local effectiveness of the well contact and reducing the single-event-induced N-well potential modulation, parasitic amplification, and charge sharing [3], [5]- [7], and the addition of a N-well stripe implant between the NMOS devices, which isolates the P-wells and eliminates charge sharing (similar to a guard ring [1], [6]). In the latter case, the isolated P-wells remain contacted through the epi substrate.…”

Section: B Tcad Mechanism and Mitigation Simulationsmentioning

confidence: 99%

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

Kelly

Alles

Ball

et al. 2014

IEEE Trans. Nucl. Sci.

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The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps.Index Terms-Charge sharing, radiation hardening by design, RHFGPA, single event effects.

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Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes

Cited by 8 publications

References 12 publications

Alpha-particle and neutron-induced single-event transient measurements in subthreshold circuits

Alpha-particle and neutron-induced single-event transient measurements in subthreshold circuits

Impact of gate shapes on single event transients

Mitigation of Single-Event Charge Sharing in a Commercial FPGA Architecture

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