Effects of Die-Attach Quality on the Mechanical and Thermal Properties of High-Power Light-Emitting Diodes Packaging

Abstract

The reliability of high-power light-emitting-diode (LED) devices strongly depends on the die-attach quality because voids may increase junction temperature and total thermal resistance of LED devices. Die-attach material has a key role in the thermal management of high-power LED package by providing low-contact thermal resistance. Thermal and mechanical analyses were carried out by experiments and thermal simulation. The quantitative analysis results show that thermal resistance of die-attach layer (thermal resistance caused by die-attach material and voids in die-attach layer) plays an important role in total thermal resistance of high-power LED packaging according to the differential structure function of thermal transient characteristics. The increase of void fraction in die-attach layer causes the increases of thermal resistance of die-attach layer; the thermal resistance increased by 1.95 K/W when the void fraction increased to 62.45%. The voids also make an obvious influence on thermal stress and thermal strain of chip; the biggest thermal stress of chip was as high as 847.1 MPa compared to the 565.2 MPa when the void fraction increases from being void-free to 30% in the die-attach layer.

Boronic Acid-Based n-Type Semiconductor for Electronic Device Application

“…Good thermal features of the active layer can reduce premature device failures and increase the lifetime. 29 The variation in the mass of SHB with increasing temperature was examined, and the respective thermogram is presented in Fig. 3b, denoting good thermal stability up to 200°C in concordance with that of previous literature.…”

Investigation on effects of solder paste voids on thermal and optical performance of white high-power surface-mounted device LEDs

“…The thickness of solder layer is kept constant using same stencil thickness, and its height was controlled using the stencil printing by multiple printing approach (He et al , 2017). To get lower void fraction for LED1, the height of the SP layer is higher compared to others and the solder pressed hardly during the soldering process.…”

“…The fraction of voids in the SP layer was controlled using the printing press, placement force and solder coverage area during the soldering process, which are considered the typical factors that affect the formation of voids in solder (Sweatman et al , 2016). It was proved in He et al (2017) that the bigger bonding pressure causes a decrease in the voids fraction and thickness of the DA layer and consequently improves the thermal resistance of bonding layer. The SP was pressed harder (bigger pressure) in the printing process to ensure less voids but pressed softer (less pressure) to create relatively more voids.…”

“…Afterward, the heat from the LED package conducted through the solder layer to the substrate and finally to the environment by air convection. If the solder layer is entrapped a lot of voids, the heat conduction path will be seriously affected, as shown in Figure 2 (He et al , 2017). Accordingly, the junction temperature increased that results in increasing thermal resistance and failure of the entire LED package (Otiaba et al , 2013).…”

Multiple Heat Source Thermal Modeling and Transient Analysis of LEDs

“…We use simulated SFs to quantify the impact. The DAL is the most significant contributor to total of LED packages [38,39]. The partial of a DAL can reach up to tens of K/W for a single die MP LEDs package ( Figure 2), while the partial values of other heat path structures as sapphire crystal and thermal pad are below 10 K/W.…”