Effects of defect creation on bidirectional behavior with hump characteristics of InGaZnO TFTs under bias and thermal stress

Abstract

We investigated the hump characteristics of amorphous indium-gallium-zinc oxide thin-film transistors. The device showed a field effect mobility of 24.3 cm 2 V %1 s %1 , a threshold voltage (V th ) of 4.8 V, and a subthreshold swing of 120 mV/dec. Under positive gate bias stress, V th showed bidirectional shift with a hump. V th was positively and negatively shifted in the above-threshold and subthreshold regions, respectively. At high temperatures, V th was more positively shifted without bidirectional shift. Under simultaneous drain bias stress (V DS,stress ), the hump was maintained. However, the bidirectional shift was not observed with an increasing V DS,stress . The hump and positive shift are related to the defect creation of the shallow donor-like and deep-level acceptor-like states, respectively. We performed a two-dimensional device simulation to further investigate this phenomenon. By varying the peak values of the Gaussian shallow donor-like and deep acceptor-like states, we qualitatively confirmed the relationship between the two states and transfer curve changes.

Performance Investigation of an n-Type Tin-Oxide Thin Film Transistor by Channel Plasma Processing

“…In addition, the hump was also affected by the density of the channel traps, which were mainly defined as the acceptor-like states in the simulation. As the channel trap density increased, the above-threshold region shifted more in the positive direction, which agreed well with the previous report [21]. Figure 3(a), (b), (c) and (d) show the extracted I on /I off , SS μ FE and N it values of the simulated n-type SnO x TFT devices as a function of the channel trap density.…”

“…For the fabricated n-type SnO x TFT device, an N it value of 1.1x10 13 cm −2 was obtained, resulting in a moderate SS of 405 mV/dec. Besides, it was found that a hump occurred in the transfer curve for the n-type SnO x TFT device, which could be due to the deep-level acceptor-like states induced by the oxygen plasma process [21].…”

Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

“…Generally, the positive shi of V TH under PBTS conditions is explained by the electron trapping mechanism within GI and/or at the interface between the GI and IGZO channel layers. 26,27 However, DV TH values for TFTs using ALD IGZO channels were measured as À0.5, À1.8, and À6.9 V in the PBTS tests at temperatures of 40, 60, and 80 C, respectively. There were no marked variations in the PBTS instabilities in the linear region of I DS (V DS ¼ 0.5 V).…”

TCAD Simulation of Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistors

“…This hump has been reported on several scenarios, and many different explanations have been reported so far. Some authors report it as a result of an effect of shallow donor-like states creation in the semiconductor [6]. Fig.…”

“…Instabilities in oxide TFTs can be further investigated with TCAD, by implementing charge-trapping and defect creation in the simulations, allowing to understand the specific physical causes of degradation in TFTs, typically associated with Gate/Drain Bias Stress, illumination and temperature. Correlations between the defect-creation and the device performance degradation have been reported [6], with localization of defect creation being also investigated by means of simulations [7]. Some effects that limit device performance are related to device architecture, as parasitic capacitances that limit the maximum operation frequency, and short channel effects (SCE), which limit the scalability of the technology.…”