Effects of CMOS process fill patterns on spiral inductors

Chen, Chang‐Lee

doi:10.1002/mop.10790

Cited by 10 publications

(8 citation statements)

References 5 publications

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“…In order to accurately understand the physical behavior of the Faraday cage, Fig. 9(a) shows a simplified equivalent circuit used for modeling each single spiral inductor [12]. The spiral inductor structure is represented by an inductance L s , a series resistance R s , the coupling capacitance C c and resistance R c .…”

Section: Lumped Modeling Of Noise Coupling Effectsmentioning

confidence: 99%

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs

Cai

Harjani

2008

2008 IEEE Custom Integrated Circuits Conference

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Faraday cages have traditionally been used to provide isolation from electromagnetic fields. In this paper, we describe the use of Faraday cages for reducing crosstalk in 3D ICs. We validate our methodology with a combination of simulation and measurements from fabricated prototype designs. Measurement and simulation results show that the crosstalk between the transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday cage in combination with tierto-tier isolation, which is one of best performance reported so far. We further develop a lumped equivalent model for crosstalk with and without a Faraday cage. There is good agreement between measurement, 3D electromagnetic simulation and lumped circuit simulation. IEEE 2008 Custom Intergrated Circuits Conference (CICC)978-1-4244-2018-6/08/$25.00 ©2008 IEEE 22-1-1

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Section: Lumped Modeling Of Noise Coupling Effectsmentioning

confidence: 99%

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs

Cai

Harjani

2008

2008 IEEE Custom Integrated Circuits Conference

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“…The power dissipated in the metal fills is an additional loss mechanism for the inductor and thus reduces its . However, (5) illustrates that this extra loss can be significantly reduced by using metal fills with small fill cell sizes. The equations in (5) provide guidelines on device sizing inside an inductor but are not sufficiently accurate for quantitative estimates.…”

Section: Metal Fill Test Structuresmentioning

confidence: 99%

Design of Components and Circuits Underneath Integrated Inductors

Zhang

Kinget

2006

IEEE J. Solid-State Circuits

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In this paper, we present a study of the eddy current effect of devices placed underneath and inside an on-chip inductor. We verified the performance of such area-saving structures through electromagnetic (EM) simulations and measurement of test structures. We used layout techniques to minimize eddy current loss and magnetic coupling between the devices and the inductor, and constructed a complete voltage-controlled oscillator (VCO) inside an inductor. Measurement results show that this compact VCO has an equal performance in phase noise and output power as compared to a traditional VCO while reducing the area by about 50%. The techniques presented in this paper are general and can be implemented in most layouts without extra post-processing steps. Index Terms-Eddy current, layout, metal fill, radio frequency integrated circuits (RFIC), voltage-controlled oscillator (VCO). I. INTRODUCTION S PIRAL on-chip inductors are found in many radio frequency (RF) transceivers and are the essential components for low noise amplifiers, filters, voltage-controlled oscillators (VCO), and other RF building blocks. On-chip inductors are indispensable in RF circuits because their alternatives use active components which are noisy and consume too much power. However, on-chip inductors have the drawback of consuming large die area, which translates to higher cost. An inspection of existing RF integrated circuit (RFIC) layouts (for example, the GPS receiver shown on the cover of [1] and the die photo of a transceiver in [2]) indicates that the on-chip inductors used in the RF sections of the integrated circuits dominate the die area of the chip. This trend will become even more significant in future process nodes since passive devices do not significantly reduce in size with process geometry scaling in contrast to their active counterparts. Up to now, the real estate underneath the inductors has not been utilized because of the concern that components under the inductor would degrade the quality factor, , of the inductor through eddy current loss. However, if the size of the devices placed in and around the inductor is kept small, the induced eddy current loops are localized in small regions which keeps the losses to a minimum. Furthermore, by carefully planning the current paths of the devices, magnetic coupling between the device currents and the inductor currents can be reduced. With these two properties in mind, we explore Manuscript

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“…The presence of conducting fill underneath an inductor naturally changes the electromagnetic field distribution, and hence the characteristic inductor's parameters. The effect of the dummy metal pattern on the same metal layer as the on-chip inductor [5] and under the spiral [6] with different pattern and configuration of the fill has already been reported. The most significant influence of the metal fill on the inductor performance is the change in the self resonance frequency which has the highest value for an inductor with no fill.…”

Section: Introductionmentioning

confidence: 96%

Simplified Model of a Layer of Interconnects under a Spiral Inductor

Holik¹,

Drysdale²

2011

JEMAA

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An empirical effective medium approximation that provides a homogeneous equivalent for a layer of interconnects un-derneath a spiral inductor is presented. When used as part of a numerical 3D model of the inductor, this approach yields a faster simulation that uses less memory, yet still predicts the quality factor and inductance to within 1%. We expect this technique to find use in the electromagnetic modeling of System-on-Chip

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Effects of CMOS process fill patterns on spiral inductors

Cited by 10 publications

References 5 publications

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs

Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs

Design of Components and Circuits Underneath Integrated Inductors

Simplified Model of a Layer of Interconnects under a Spiral Inductor

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