2011
DOI: 10.1016/j.microrel.2011.07.018
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Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

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Cited by 51 publications
(39 citation statements)
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“…DV th0 increases from 3.64 V to 4.9 V as the channel length decreases. The s value decreases from 9043 s to 4760 s as channel length decreases which is consistent with an increase of the charge trapping rate, because the smaller s causes the faster charge trapping time [19].…”
Section: Gs+ Stress At Various Channel Lengthssupporting
confidence: 72%
“…DV th0 increases from 3.64 V to 4.9 V as the channel length decreases. The s value decreases from 9043 s to 4760 s as channel length decreases which is consistent with an increase of the charge trapping rate, because the smaller s causes the faster charge trapping time [19].…”
Section: Gs+ Stress At Various Channel Lengthssupporting
confidence: 72%
“…Amorphous oxide transistors have exhibited improvement of electrical characteristics and negative shift of threshold voltage (and turn-on voltage) according to the increase of carrier concentration unlike the Si-based TFTs. 16,17 Therefore, the turn-on voltages of ZTO and SZTO TFTs have been controlled by changing channel thickness. The inverter consisting of all n-type transistors can be implemented by adopting different V on of ZTO and SZTO TFTs.…”
Section: -13mentioning
confidence: 99%
“…For the display technology, the trend has always been toward high compactness, which necessitates the understanding of how the activelayer thickness affects TFT performance. In this regard, recent reports on a-IGZO TFTs have stressed the importance of the a-IGZO layer thickness in TFT operation [2], [3] and stability [4]. Barquinha et al reported operation characteristics of thin a-IGZO TFTs and observed deterioration in performance of TFTs with 5-nm-thick a-IGZO layers [2].…”
Section: Introductionmentioning
confidence: 99%