Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal–oxide–semiconductor field-effect transistors

Abstract

Using a dual spacer consisting of 50% SiO 2 and 50% HfO 2 , the ratio of the on-state current/the off-state current in the order of 10 6 is achieved for the explored devices. Based on the experimentally validated simulation, the result indicates that the variation of gate-capacitance is significant owing to the sizeable parasitic capacitance resulting from the spacer. The role of the spacer acts as the parallel plate capacitor, the amount of gate capacitance will be increased largely with the HfO 2 due to its high parasitic capacitance. For the devices without any spacers, induced by a donortype single charge trap (SCT), the statistically calculated highest amplitude of random telegraph noise (RTN) is 2.32%. It occurs when the SCT locates in the middle of the channel due to the high occurrence of capture and emission for SCT under low gate voltage. Notably, for devices with considerable spacers, the RTN can be significantly suppressed (⩽1%).

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

“…Regarding layout efficiency, power consumption, and scalability in CMOS design, vertical GAA Nanowire FETs outperform FinFETs and even horizontal GAA Nanowires [11]. Several channels can be used in GAA FETs, which are silicon nanowires/nanosheets stacked vertically, to achieve the necessary performance in applications like DC, analog, and RF [12], [13]. In NW-FET, it is necessary to have a wide gap between two adjacent NWs, which poses problems in the fabrication, and the aspect ratio of the channel stack is increased.…”