Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors

Kola, Sekhar Reddy; Li, Yiming; Chuang, Min-Hui

doi:10.1109/isqed57927.2023.10129391

Cited by 4 publications

(4 citation statements)

References 28 publications

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“…Our mobility models are comprehensive and encompass several crucial components [23]. These models include the Philips unified model, high-field saturation model, thin layer model, and Lombardi high-k mobility model, which address phonon and Coulomb scatterings at the channel/insulator interface [19], [58]. To incorporate quasi-ballistic effects, we have integrated the low-field ballistic mobility model into our simulations.…”

Section: Overview Of Device and Variability Modelingmentioning

confidence: 99%

“…NSFET devices can have different sources of device variability. For this study, we considered the channel length (L), nanosheet thickness (TNS), and nanosheet width (WNS) that have a significant effect on the electrical characteristics of the devices [58]. The device parameters and their mean and standard deviation are L is 16 and ±3, W is 25 and ±3, and T is 5 and ±2.…”

Section: Overview Of Device and Variability Modelingmentioning

confidence: 99%

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A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Butola,

Li,

Kola

2023

IEEE Open J. Nanotechnol.

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Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates.

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Section: Overview Of Device and Variability Modelingmentioning

confidence: 99%

Section: Overview Of Device and Variability Modelingmentioning

confidence: 99%

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Butola,

Li,

Kola

2023

IEEE Open J. Nanotechnol.

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“…Hence, it is imperative to acknowledge that process variations wield a substantial influence on the holistic operational performance of circuits employing these devices. On the other hand, process variation effect (PVE) and intrinsic parameter fluctuation (IPF) consists of work function fluctuation (WKF), random dopant fluctuation (RDF), and interface trap fluctuation (ITF), are crucial in design and fabrication of CMOS devices [6]- [25]; in particular, for emerging CFET devices [26]- [28]. For examples, [7]- [9], [9]- [14], [14]- [19], and [13], [14], [20]- [25], were reported for planar MOSFETs, FinFETs, GAA nanowire MOSFETs, and GAA NS MOSFETs, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…These variations serve as a formidable barrier to the continued scaling of technology nodes, exerting their influence on critical aspects including SCE, timings, and power consumption parameters. Two factors of PVE: line edge roughness and gate edge roughness were individually studied by Yang et al for CFETs [26], [28]; however, impacts of PVE on electrical characteristic and power fluctuations have not been well examined yet for CFET devices and circuits. Thus, it will be an interesting study for us to statistically explore device characteristics and power fluctuations of CFETs induced by various factors of PVE.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Kola,

2023

IEEE Open J. Nanotechnol.

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Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously.

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Characteristics Fluctuation of Sub-3-nm Bulk FinFET Devices Induced by Random Interface Traps

Kola,

Chuang,

2023

2023 IEEE 23rd International Conference on Nanotechnology (NANO)

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Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors

Cited by 4 publications

References 28 publications

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Characteristics Fluctuation of Sub-3-nm Bulk FinFET Devices Induced by Random Interface Traps

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