Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

Berg, Melanie D.; Poivey, C.; Petrick, David; Espinosa, Daniel Vallo; Lesea, A.; LaBel, K.A.; Friendlich, M.; Kim, H.; Phan, Anthony M.

doi:10.1109/tns.2008.2001422

Cited by 115 publications

(54 citation statements)

References 6 publications

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“…These primitives are theirselves implemented in the programmable fabric, so they are also susceptible to radiation. Although faulttolerant implementations of internal scrubbers have been proposed [9], external scrubbers are typically more reliable [10]. In this work, only external scrubbers will be considered.…”

Section: Internal Versus External Scrubbingmentioning

confidence: 99%

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

Herrera-Alzu

López‐Vallejo

2011

Lecture Notes in Computer Science

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Abstract. SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory.

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Section: Internal Versus External Scrubbingmentioning

confidence: 99%

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

Herrera-Alzu

López‐Vallejo

2011

Lecture Notes in Computer Science

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“…XHWIF interface port and external SelectMAP configuration port were required to perform fault injection in this platform. Our approach, however, does not need external controller to manage SelectMAP port or XHWIF port (M. Berg, 2008Berg, , p. 2259Berg, -2266. It is a succinct platform that all components are in side a single FPGA to run high performance fault injection emulation.…”

Section: Introductionmentioning

confidence: 99%

A Kind of Low-cost Non-intrusive Autonomous Fault Emulation System

Zhang

Jun²,

Yu³

2011

CIS

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SRAM-Filed Programmable Gate Arrays (FPGA) have become one of the most important carriers of digital electronic system because of its many inborn advantages. However, as manufacture of Integrated Circuit evolves towards Very Deep Sub-Micron technology, FPGA designers must be careful of circuit's Single Event Upset (SEU) susceptibility when used in hostile environment, such as avionics and space applications where reliability is vital. We proposed a SEU-fault emulation platform to evaluate circuit's SEU mitigation performance. The platform does not need any external circuit or micro controller to manage fault emulation process compared with existing approach. Source codes of Circuit Under Test (CUT) do not need to be modified or intruded with any component. It is a non-intrusive testing. Communication between host-computer and emulation board is minimized to accelerate fault injection speed. Experimental result shows that a single fault injecting (including Multi-Bits-Upset) only costs 29us. A circuit state reloading technology is exploited to increase emulation efficiency. Moreover, in the field of evolvable hardware, genetic operations can be reconfigured and its fitness can be evaluated on-line using the proposed fast dynamic reconfiguration method, which is useful for implementing self-repair and self-evolutionary hardware.

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“…In essence, concurrent detection provides the mentioned low latency of detection, as it happens during normal operation of the system.They enable the system to react to errors, not originated by ill-design but operating conditions, while running and in an automated or assisted way. Different base techniques have been employed to perform detection concurrently: in space redundancy options are replicas comparison [20,166] or tailored function checkers [167,173,152], in information redundancy the use of coding [74,19,174,21,61,179], and in temporal redundancy the re-execution and comparison [93,138,47].…”

Section: Detectionmentioning

confidence: 99%

“…For instance, when the fault affects the configuration memory, where logic functions implemented by the device are set, the problem will remain until a rewrite operation of that memory takes place. For that reason modern FPGAs usually implement a scrubbing engine, which continuously checks and rewrites as needed the different data frames to recover correct values when these have been altered [19]. Likewise, a fault can also affect an element in the fabric (logic) of the device.…”

Section: Fault Recoverymentioning

confidence: 99%

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New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs

García¹

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"The problem with the world is that the intelligent people are full of doubts, while the stupid ones are full of confidence." Charles Bukowski AgraïmentsVolguera començar agraïnt totes aquelles persones que han fet possible que esta tesi esdevinguera realitat. A totes aquelles persones i que m'han acompanyat durant tot este temps, amb el seu suport tècnic, lingüístic, físic, econòmic o psicològic. Primerament, agrair els meus directors els doctors David de Andrés i Juan CarlosRuiz per la seua dedicació, suport i ànim durant estos anys. Heu sigut de gran ajuda. També al professor Pedro Gil per confiar en mi i donar-me el recolzament econòmic i científic per portar a terme el projecte.Així mateix, també volguera tenir unes paraules per als meus companys del grup de Sistemes Tolerants a Fallades (STF) i en especial als del laboratori: el ja doctor Jesus Friginal, Miquel Martinez, Héctor Marco, Javier Cancio i Antonio Bustos. Haveu sigut els millors, i junts hem passat molt bons moments. També agrair els companys de l'estada a Edinburgh Félix Casado i Ali Ebrahim, i molt especialment als del Barcelona Supercomputing Center Carles, Jaume, Mikel, Javi, Maria, David, Roberto, Milos, Mladen, Suzanna, Quixiao, Leonidas i la resta del grup CAOS per fer-me sentir com a casa.Per descomptat que no només he rebut suport dels companys de recerca. Per això he d'esmentar la meua estimada Sara, per donar-me tot el suport i l'estima possibles i impossibles, i els meus pares i germans, perquè sempre han estat fentme costat i m'han animat a seguir estudiant per comprendre millor el món que ens envolta.Finalment a les persones de la Universitat en general, i del món científic en particular, a la vocació dels quals devem que el sistema continue funcionant.Jaume.v SumariLa rellevància que l'electrònica adquireix en la seguretat dels productes ha crescut inexorablement, puix cada volta més aquesta abasta una major influència en la funcionalitat dels mateixos. Però, per descomptat, aquest fet ve acompanyat d'un constant necessitat de majors prestacions per acomplir els requeriments funcionals, mentre es mantenen els costos i consums en uns nivells reduïts. Donat aquest escenari, la indústria està fent esforços per proveir una tecnologia que complisca amb totes les especificacions de potència, consum i preu, tot a costa d'un increment en la vulnerabilitat a diversos tipus de fallades conegudes, i a la introducció de nous tipus.Per oferir una solució a les noves i creixents fallades als sistemes, els dissenyadors han recorregut a tècniques tradicionalment associades a sistemes crítics per a la seguretat, que en general oferixen resultats sub-òptims. De fet, les arquitectures empotrades modernes oferixen la possibilitat d'optimitzar les propietats de confiabilitat en habilitar la interacció dels nivells de hardware, firmware i software en el procés. Tot i això eixe punt no està resolt encara. Es necessiten avanços a tots els nivells en l'esmentada direcció per poder assolir els objectius d'una tolerància a fallades flexible, robusta, resili...

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Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

Cited by 115 publications

References 6 publications

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

A Kind of Low-cost Non-intrusive Autonomous Fault Emulation System

New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs

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