Effective model-based SRAF placement for full chip 2D layouts

Jayaram, Srividya; LaCour, Pat; Word, James; Tritchkov, Alexander

doi:10.1117/12.2011611

Cited by 5 publications

(5 citation statements)

References 4 publications

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“… OPC and assist options [13][14][15] : We included several End-of-Line (EOL) structures in our OPW evaluation, and for the larger EOL gaps, we showed (section 4.2) the importance of the assist-placement in or around the gap. This demonstrates that -if one wants to use rule-based assist placement -the rule would need to specify how to do this.…”

Section: Discussionmentioning

confidence: 99%

“…For a line-or trench-like patterns as our M1 application, making an assist rule is quite feasible. In view of observations as the ones shown in Figure 6 (for which, we are in variance with Reference [14]), we decided to invest in a good assist rule, that would be based on both experimental data and rigorous simulation (S-Litho), and which would incorporate information on assist printing from printed wafers. First of all, let's specify that an assist rule is essentially a table that tells how many assists, at which positions and with which width are to be placed in a certain space between two main features.…”

Section: Opc and Assist-placement Optionsmentioning

confidence: 99%

“…As an intermediate step in generating model-based assist-placement, MentorGraphics uses what they call a 'gradient map' [14] . An example is shown in Figure 13.b.…”

Section: Limiter #2: Assist Solutionsmentioning

confidence: 99%

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Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

et al. 2014

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A Metal1-layer (M1) patterning study is conducted on 20nm node (N20) for random-logic applications. We quantified the printability performance on our test vehicle for N20, corresponding to Poly/M1 pitches of 90/64nm, and with a selected minimum M1 gap size of 70nm. The Metal1 layer is patterned with 193nm immersion lithography (193i) using Negative Tone Developer (NTD) resist, and a double-patterning Litho-Etch-Litho-Etch (LELE) process. Our study is based on Logic test blocks that we OPCed with a combination of calibrated models for litho and for etch. We report the Overlapping Process Window (OPW), based on a selection of test structures measured after-etch. We find that most of the OPW limiting structures are EOL (End-of-Line) configurations. Further analysis of these individual OPW limiters will reveal that they belong to different types, such as Resist 3D (R3D) and Mask 3D (M3D) sensitive structures, limiters related to OPC (Optical Proximity Corrections) options such as assist placement, or the choice of CD metrics and tolerances for calculation of the process windows itself. To guide this investigation, we will consider a 'reference OPC' case to be compared with other solutions. In addition, rigorous simulations and OPC verifications will complete the after-etch measurements to help us to validate our experimental findings.

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Section: Discussionmentioning

confidence: 99%

Section: Opc and Assist-placement Optionsmentioning

confidence: 99%

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Metal1 patterning study for random-logic applications with 193i, using calibrated OPC for litho and etch

et al. 2014

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“…A careful adjustment of local SBs around the weak points will significantly increase the local process windows (PW) and fix the weak points. In order to overcome the incomplete coverage of rule-based (RB) SBs, the model-based (MB) SBs [14][15] might provide a solution. Srividya Jayaram and co-workers [14] have applied MB SB and RB SB to the logic and SRAM part of a CT layout, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…In order to overcome the incomplete coverage of rule-based (RB) SBs, the model-based (MB) SBs [14][15] might provide a solution. Srividya Jayaram and co-workers [14] have applied MB SB and RB SB to the logic and SRAM part of a CT layout, respectively. The MB SBs can better improve the PWs for the logic part that possesses highly irregular geometries, as compared to the RB SBs, while its computational cost is quite acceptable.…”

Section: Introductionmentioning

confidence: 99%

The comparison of the effectiveness of model-based SRAFs and rule-based SRAFs

2016

2016 China Semiconductor Technology International Conference (CSTIC)

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The SRAFs that are usually in the form of scattering bars (SBs) are inserted to the contact layer to maintain proper local pattern densities, ensuring a good resolution on a full chip scale. There exist 2 practical addition schemes of SBs; namely, the rule-based (RB) SB and model-based (MB) SB. The RB SBs are set up by the inspection of local pattern geometries and their effectiveness heavily relies on engineers' experiences. In contrast, the MB scheme adds the SBs in accordance to the computed contrasts of contact edges. It is fully environment adaptive and can hence save a huge amount of human efforts. Moreover, the MB scheme is capable of taking the process window (PW) conditions into account so that DOF (depth of focus) and EL (energy latitude) can be optimized on a full chip scale due to the added SBs. Since the PW conditions are not explicitly included in the RB scheme, it is expected that the MB SBs should have a better performance than the RB SBs. Using a real chip as a test case, we have found that the MB scheme can better control the PV (process variability) band width though, the overall performances of these 2 SB schemes are comparable. However, optimizing a limited number of adjustable parameters can further improve the performance of MB SBs. Both schemes yield some weak points. The weak points that are resulted from one scheme can be fixed by the other scheme. Hence, these 2 schemes are complementary to each other. This inspires us to incorporate the MB SB into the post-OPC repair flow.

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