Effective exploitation of SIMD resources in cross-ISA virtualization

Wu, Jin; Dong, Jian; Fang, Ruili; Zhao, Ziyi; Gong, Xiaoli; Wang, Wenwen; Zuo, Decheng

doi:10.1145/3453933.3454016

Cited by 6 publications

(3 citation statements)

References 49 publications

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“…Wu et al [38] focused on reducing the majority of writes introduced by DBT, introduced a flag to indicate where the latest value of an emulated guest register is placed, and mapped the guest register to host general-purpose registers directly. Wu et al [42] bridged the utilization gap and unleashed the full potential of host SIMD resources and emulated the guest general-purpose registers with host SIMD registers to reduce the memory access. Fu et al [41] recompiled the hotness code to improve translation code quality.…”

Section: Related Workmentioning

confidence: 99%

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Xie,

Luo,

Tian

et al. 2024

Electronics

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The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.

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Section: Related Workmentioning

confidence: 99%

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Xie,

Luo,

Tian

et al. 2024

Electronics

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“…Previous works have proposed many optimization methods for DBT, such as more fully exploiting the various features of the CPU 6,7,8 and the potential contained in hardware resources 9 , reusing translation codes 10,11 and generating higherquality translation codes 12 , etc. These studies have greatly improved the performance of the binary translation system.…”

Section: Dynamic Binary Translation (Dbt)mentioning

confidence: 99%

“…There are also some other DBT-related optimizations 9,11,12,24 . In general, it is possible to for our approach to cooperate with these schemes to further improve the emulation efficiency.…”

Section: Related Workmentioning

confidence: 99%

Efficient condition code emulation for dynamic binary translation systems

Zeng

Xie

Dong

et al. 2023

Third International Symposium on Computer Engineering and Intelligent Communications (ISCEIC 2022)

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Dynamic binary translation is widely used in cross-ISA (Instruction Set Architecture) binary migration. With the technology, computers can directly execute programs compiled in other platforms, which helps to reduce the cost of software migration between different architectures. Efficient condition code emulation is critical for achieving higher performance. However, existing binary translation systems typically have to emulate the guest flags register with memory variables to hide the ISA difference, which is less-efficient due to code expansion. In this paper, we propose a way to substitute guest conditional instructions with counterpart instructions from the host ISA to achieve higher performance in flags register emulation. We recognize flag-defining and flag-checking instructions respectively through scanning the guest code sequence and then reproduce the condition pattern in the dynamically generated host code with the corresponding flag-related instructions in the host ISA. The evaluation results show that our approach manages to reduce the dynamically generated host instructions by 7.53% and improve the performance by 14.3% on average.

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