Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores

Abstract

Abstract. The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and partitioned register file structures in addition to a heterogeneous clustered data-path architecture to attain low power consumption and a smaller die. As part of an effort to overcome the new challenges of code generation for the PAC DSP, we have developed a new register allocation scheme and other retargeting optimization phases that allow the effective generation of high quality code. Our preliminary experimental results indicate that our developed compiler can efficiently utilize the features of the specific register file architectures in the PAC DSP. Our experiences in designing compiler support for the PAC VLIW DSP with irregular resource constraints may also be of interest to those involved in developing compilers for similar architectures.

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

“…Functional units are grouped into two clusters: one cluster for two-issue memory operations and the other for fourissue arithmetic operations. The PAC-DSP core provided by the Industry Technology Research Institute (ITRI) [Lin et al 2008] is also a clustered architecture using a pingpong register file design-a register file with reconfigurable connection to functional units-for intercluster data exchange with a limited amount of access ports.…”

“…A DSP core is mainly used to process streamed data with a kernel loop. Various researchers have proposed software pipelining algorithms to improve the performance of clustered VLIW architectures [Akturan and Jacome 2001;Qian et al 2002aQian et al , 2002bZalamea et al 2001]. This article redefines the instruction scheduling problem from an alternative viewpoint: deadline-constrained energy optimization for energy-proportional computing.…”

“…Digital Signal Processors (DSPs) with Very Long Instruction Word (VLIW) architectures are widely used in embedded systems and multimedia systems-on-chip (SoCs) [Philips 2011;Texas Instruments 2011]. Assisted by the compiler to exploit instruction-level parallelism, a VLIW DSP has multiple execution slots to provide high-performance arithmetic computing.…”

“…The power dissipated in the global register file of an N-issue VLIW processor is on the order of O(N 3 ) [Rixner et al 2000]. Major VLIW DSPs employ some forms of distributed register files architectures to reduce the register file power [Freescale Semiconductor 2008;Lin et al 2008;Texas Instruments 2005]. Various researchers have also proposed a variety of compiler optimization technologies for distributed register files architectures [Akturan and Jacome 2001;Aleta et al 2007;Qian et al 2002aQian et al , 2002bZalamea et al 2001].…”

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

“…The ORC frontend helps to generate the intermediate representation, WHIRL, with five representation levels from "very high" to "very low", where various targetindependent optimizations are performed, such as control flow optimization, extended basic block (peephole) optimization, integrated global/local scheduling, and loop transformation at the "very low" level. We have developed specific optimization techniques in the backend for PACDSP, including copy propagation for irregular register files [17], optimal local register file assignment based on simulation annealing (SA-LRFA) [18], ping-pong aware & local favorable register file assignment (PALF-LRFA) [19], and local-conscious & global register file assignment (LC-GRFA) [20], etc. LC-GRFA is the most important optimization, which minimizes data communication costs between various registers.…”