Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages

Khor, C. Y.; Abdullah, Moha Asri; Abdullah, M. Z.; Mujeebu, M. Abdul; Ramdan, Dadan; Majid, M. F. M. A.; Ariff, Zulkifli Mohamad

doi:10.1007/s00231-010-0661-z

Cited by 27 publications

(13 citation statements)

References 18 publications

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“…At 3.2s, the filling of the mould cavity is nearly completed. The faster flow front totally covered the chip and resulted in the air trap beneath the chip [10]. The variations of the flow-induced forces on the chip caused the deformation around the middle region, which has no solder bump supported.…”

Section: Viscosity Modelsmentioning

confidence: 99%

Influence of Material Properties on the Fluid-Structure Interaction aspects during Molded Underfill Process

et al. 2017

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Abstract. This paper presents the investigation of the effects of epoxy moulding compound' (EMC) viscosity on the FSI aspects during moulded underfill process (MUF). Finite volume (FV) code and finite element (FE) code were connected online through the Mesh-based Parallel Code Coupling Interface (MpCCI) method for fluid and structural analysis. The EMC flow behaviour was modelled by Castro-Macosko model, which was written in C language and incorporated into the FV analysis. Real-time predictions on the flow front, chip deformation and stress concentration were solved by FV-and FE-solver. Increase in EMC viscosity raises the deformation and stress imposed on IC and solder bump, which may induce unintended features on the IC structure. The current simulation is expected to provide the better understandings and clear visualization of FSI in the moulded underfill process.

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Section: Viscosity Modelsmentioning

confidence: 99%

Influence of Material Properties on the Fluid-Structure Interaction aspects during Molded Underfill Process

et al. 2017

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“…The volume of fluid (VOF) model in FLUENT 6.3.26 is utilized to simulate the process [6]. EMC types are set at different parameters, as shown in Table 1.…”

Section: Numerical Simulation 221 Simulation Model and Boundary Conmentioning

confidence: 99%

“…The PBGA chip package model used in the present study and its boundary conditions are shown in Figure 1a. The boundary and initial conditions are used in the calculation are as follows [6,7] …”

Section: Numerical Simulation 221 Simulation Model and Boundary Conmentioning

confidence: 99%

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Plastic Ball Grid Array Encapsulation Process Simulation on Rheology Effect

2011

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Abstrak Rangkaian elektronik terpadu harus dikemas untuk perlindungan dari pengaruh lingkungan seperti temperatur, tekanan dan benturan. Makalah ini menyajikan analisa visualisasi aliran fluida pada proses pengemasan (encapsulation process) IntroductionThe EMC rheology properties play an important role during the encapsulation process. It is because the final physical properties of EMC and processing rely on it. Rheology is defined as the science of flow and deformation of matter [1]-[4]. The most common models of rheology are the Castro-Macosko model. It is especially used in thermoset polymer rheology [4].The effect of gaps between die top and mold cap surface and between adjacent dies on EMC rheology during stacked-chip scale packages (S-CSP) encapsulated was studied by Abdullah MK et al. [4]. Rheokinetic simulation of mold filling behavior, mold void and wire sweeping dependences of gate size was analyzed by Lee MW et al. [5].In the present study, the computational fluid dynamic (CFD) code FLUENT 6.3 [6] is used to analyze the effect of rheology on the flow behavior of the encapsulation process of PBGA. The three dimensional models are developed and analyzed by using finite volume method. Flow behavior of encapsulant is modeled by Castro-Macosko with curing kinetic model by using user

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“…However, the occurrence of void formation reduces package reliability during the encapsulation process. This problem was mentioned in various IC encapsulation processes, such as the thin quad flat package (TQFP) [3,4], TSOP II 54L LOC [5,6], stacked-chip scale package (S-CSP) [7][8][9][10], mold array package (MAP) [11], and molded underfill [12].…”

Section: Introductionmentioning

confidence: 99%

Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

Khor

Abdullah

Ariff

et al. 2012

International Communications in Heat and Mass Transfer

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Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages

Cited by 27 publications

References 18 publications

Influence of Material Properties on the Fluid-Structure Interaction aspects during Molded Underfill Process

Influence of Material Properties on the Fluid-Structure Interaction aspects during Molded Underfill Process

Plastic Ball Grid Array Encapsulation Process Simulation on Rheology Effect

Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

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