Effect of thermal processing on mobility in strained Si/strained Si1−yGey on relaxed Si1−xGex (x&amp;lt;y) virtual substrates

Jung, Jongwan; Yu, Shaofeng; Olubuyide, O.O.; Hoyt, Judy L.; Antoniadis, D.A.; Lee, Minjoo Larry; Fitzgerald, Eugene A.

doi:10.1063/1.1719275

Cited by 31 publications

(23 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…A promising structure for accomplishing this without imposing severe critical thickness constraints is the dual-channel heterostructure: epitaxially-grown strained-Si on compressively strained-Si Ge on a relaxed Si Ge virtual substrate [3]. Because of the high hole mobility in compressively strained-Si Ge , large hole mobility enhancements (greater than 2X) can be sustained even at high vertical field [3]- [9]. In this structure, however device characteristics including mobility and subthreshold swing depend on the strained-Si cap thickness.…”

Section: Tradeoff Between Mobility and Subthresholdmentioning

confidence: 98%

Tradeoff Between Mobility and Subthreshold Characteristics in Dual-Channel Heterostrucure n- and p-MOSFETs

Jung

Chleirigh

et al. 2004

IEEE Electron Device Lett.

View full text Add to dashboard Cite

The mobility and subthreshold characteristics of TiN-gate, dual-channel heterostructure MOSFETs consisting of strained-Si-Si 0 4 Ge 0 6 on relaxed Si 0 7 Ge 0 3 are studied for strained-Si cap layer thicknesses ranging from 3 to 10 nm. The thinnest Si cap sample (3 nm) yields the lowest subthreshold swing (80 mV/dec) and the highest hole mobility enhancement (2 3 at a vertical effective field of 1 MV/cm). N-MOSFETs show the expected electron mobility enhancement (1 8 ) for 10-and 5-nm-thick Si cap samples, which reduces to 1 6 for an Si cap thickness of 3 nm. For Si cap and gate oxide thicknesses both equal to 1 nm, simulations predict a moderate degradation in p-MOSFET subthreshold swing, from 73 to 85 mV/dec , compared to that for the Si control.

show abstract

Section: Tradeoff Between Mobility and Subthresholdmentioning

confidence: 98%

Tradeoff Between Mobility and Subthreshold Characteristics in Dual-Channel Heterostrucure n- and p-MOSFETs

Jung

Chleirigh

et al. 2004

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

“…a kT [12] where The comparison between the total interdiffusivityD total and the point-defect mediated interdiffusivityD lattice is shown in Figure 11. In the relatively lower Ge fraction region, the interdiffusion is strongly affected by the presence of strain-relaxation induced dislocations, and the interdiffusivity can be enhanced by one order of magnitude.…”

Section: The Apparent Interdiffusivities With Different R Values At 800mentioning

confidence: 99%

“…10,11 Si-Ge interdiffusion is generally undesirable as it degrades MOSFET performance by reducing strain and carrier confinement and increasing alloy scattering. 12 It also decreases photodetector efficiency, 13 and delays the lasing of Ge/Si lasers.14 Therefore, understanding Si-Ge interdiffusion behavior under different strain conditions is a topic with great technological significance. In Dong et al's previous studies, a unified Si-Ge interdiffusivity model was built for Si-Ge interdiffusion without strain over the full Ge fraction range and was validated with experiments.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Experiments and Modeling of Si-Ge Interdiffusion with Partial Strain Relaxation in Epitaxial SiGe Heterostructures

Dong

Mooney

Cai

et al. 2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Si-Ge interdiffusion and strain relaxation were studied in a metastable SiGe epitaxial structure. With Ge concentration profiling and ex-situ strain analysis, it was shown that during thermal anneals, both Si-Ge interdiffusion and strain relaxation occurred. Furthermore, the time evolutions of both strain relaxation and interdiffusion were characterized. It showed that during the ramp-up stage of thermal anneals at higher temperatures (800 • C and 840 • C), the degree of relaxation, R, reached a "plateau", while interdiffusion was negligible. With the approximation that the R value is constant after the ramp-up stage, a quantitative interdiffusivity model was built to account for both the effect of strain relaxation and the impact of the relaxation induced dislocations, which gave good agreement with the experiment data. © 2014 The Electrochemical Society. [DOI: 10.1149/2.0041410jss] All rights reserved.Manuscript submitted May 28, 2014; revised manuscript received July 9, 2014. Published July 26, 2014.As electronic and optoelectronic devices are continuously scaled down for better performance, novel materials and process techniques have been developed and integrated into the state-of-the-art semiconductor device manufacturing. In the last decades, Si 1-x Ge x (0 ≤ x ≤ 1) alloys have become key materials in electronic devices. Examples are channel materials in p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) for higher hole mobilities, 1,2 the tunneling layer in tunneling FETs, 3 and the quantum wells in resonant tunneling diodes. 4 For optoelectronic applications, SiGe alloys and Ge are also employed in modulators, 5 Ge photodiodes 6,7 and Ge/Si lasers. 8,9 Si/Si 1-x Ge x and Si 1-x Ge x /Si 1-y Ge y heterostructures with abrupt changes in Ge concentration have become key structures for many electronic and optoelectronic devices. During the fabrication of those devices, especially the ones requiring high temperature processes, unavoidably, Si and Ge atoms interdiffuse at the interface between two layers in heterostructures. This interdiffusion increases exponentially with Ge concentration and compressive stress, and also increases with ion implantation damage. 10,11 Si-Ge interdiffusion is generally undesirable as it degrades MOSFET performance by reducing strain and carrier confinement and increasing alloy scattering. 12 It also decreases photodetector efficiency, 13 and delays the lasing of Ge/Si lasers.14 Therefore, understanding Si-Ge interdiffusion behavior under different strain conditions is a topic with great technological significance. In Dong et al's previous studies, a unified Si-Ge interdiffusivity model was built for Si-Ge interdiffusion without strain over the full Ge fraction range and was validated with experiments. 15 In addition, the role of compressive strain in Si-Ge interdiffusion was modeled based on experimental data in Dong et al's recent work. 16 However, until now, there have been few studies available on Si-Ge interdiffusion behavior with partial compressive strain ...

show abstract

“…Standard Silicon oxidation produces highly reliable gate oxides at high temperatures. However, processing temperatures of s-Si are limited in comparison to standard Silicon technology due to potential diffusion of Ge and strain relaxation [3][4][5]. Excess Ge diffusion will deteriorate the Si/SiGe heterojunction layer integrity and the strained Si layer.…”

mentioning

confidence: 99%

Simulation of the electrical characteristics of MOS capacitors on strained‐silicon substrates

Kelaidis

Skarlatos

Tsamis

2008

Phys. Status Solidi (c)

View full text Add to dashboard Cite

In this work, we analyze the electrical characteristics of MOS capacitors fabricated on strained silicon substrates using the commercial software Taurus/Synopsis. The effect of various parameters such as Germanium concentration in the Si1–xGex virtual substrate, thickness of the strained‐Silicon layer, oxide thickness, fixed charge and interface trapped charge on capacitance – voltage characteristics is examined. Experimental data are compared with simulation results. A strong influence of the s‐Si/SiGe heterostructure and its proximity to the s‐Si/SiO2 on the electrical characteristics of the system exists. Oxide charge inserted into simulation in order to fit experimental data shows an increase of charge with decreasing s‐Si thickness. The effect of interface traps on simulated C‐V characteristics is identical when traps are situated in the s‐Si/SiO2 or the s‐Si/SiGe interface. When increasing the thermal budget by increasing the post oxidation annealing time, the decrease of the hump phenomenon on the C‐V curves can be attributed to the Germanium diffusion, according to simulation. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

show abstract

Effect of thermal processing on mobility in strained Si/strained Si1−yGey on relaxed Si1−xGex (x<y) virtual substrates

Cited by 31 publications

References 10 publications

Tradeoff Between Mobility and Subthreshold Characteristics in Dual-Channel Heterostrucure n- and p-MOSFETs

Tradeoff Between Mobility and Subthreshold Characteristics in Dual-Channel Heterostrucure n- and p-MOSFETs

Experiments and Modeling of Si-Ge Interdiffusion with Partial Strain Relaxation in Epitaxial SiGe Heterostructures

Simulation of the electrical characteristics of MOS capacitors on strained‐silicon substrates

Contact Info

Product

Resources

About