Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Oba, Yoshiyuki; Messemaeker, Joke De; Tyrovouzi, Anna Maria; Miyamori, Yuichi; Vos, Joeri De; Wang, Teng; Beyer, Gerald; Beyne, Eric; Wolf, Ingrid De; Croes, Kristof

doi:10.7567/jjap.54.05ee01

Cited by 16 publications

(3 citation statements)

References 28 publications

(25 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this test structure, the barrier between the TSV-fill and the bottom metal could become a flux divergence point. 28 The "as received" devices were stored in a dry N 2 -box for at about 18 months during the studies.…”

Section: Methodsmentioning

confidence: 99%

Microwave Monitoring of Atmospheric Corrosion of Interconnects

Amoah

Veksler

Sunday

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Traditional metrology has been unable to adequately address the reliability needs of emerging integrated circuits at the nano scale; thus, new metrology and techniques are needed. In this paper, we use microwave propagation characteristics (insertion loss and dispersion) to study the atmospheric interconnect corrosion under accelerated stress conditions. The results presented in this work indicate that the corrosion resilience of the test device is limited by the thermal aging of the passivation layer.

show abstract

Section: Methodsmentioning

confidence: 99%

Microwave Monitoring of Atmospheric Corrosion of Interconnects

Amoah

Veksler

Sunday

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…However, there is still a need for complete design tools and methodologies to address the challenges posed by TSV fabrication and integration in 3D ICs. Therefore, further research is needed to develop robust and efficient TSV fabrication processes, quality control techniques, and design methodologies to enable the realization of advanced 3D ICs [22,23,76].…”

Section: New Etching Techniquesmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

View full text Add to dashboard Cite

This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

show abstract

“…Figure 8 shows a cross-section of a structure where both the TSV and the micro-bump connection between different dies could be affected by electromigration failures. In fact, early data show that failures could happen in both the TSV and the micro-bump, depending on the current direction [27].…”

Section: Stacking-related Reliability Issuesmentioning

confidence: 99%

Reliability Challenges Related to TSV Integration and 3-D Stacking

Croes

Messemaeker

et al. 2016

IEEE Des. Test

Self Cite

View full text Add to dashboard Cite

Imec's view on the key reliability issues related to 3D integration is discussed. First, throughsilicon via (TSV) reliability concerns linked to thermo-mechanical stresses induced in copper and silicon and to TSV barrier/liner integrity are considered. Then, the possible impact of the TSV on the performance and reliability of nearby devices and interconnects is addressed. After that, reliability concerns related to wafer thinning and backside processing are covered by discussing the effect of stress release in exposed copper nails and the impact of backside passivation and copper contamination on devices. Finally, reliability issues caused by 3D stacking are discussed. KeywordsThrough Silicon Via; Wafer Thinning; 3D-Stacking; Reliability; IntroductionWhile IC dimension scaling leads to faster transistors, the performance of the whole integrated circuit is becoming more and more affected by the increasing signal delay associated with the cross-section scaling of on-chip and off-chip interconnects. 3D integration is one of the most promising technology candidates to mitigate the so-called interconnect bottleneck. With 3D integration, chips are stacked on top of each other, leading to a significant sleek form factor reductions [1][2]. Electrical connections between different stacked chips are made by vertical conductors, the so-called TSVs [3][4], with typical diameters and depths in the range between 2-20m and 10-100m, respectively, in leading-edge processes. TSVs can be processed at different phases of the chip fabrication. With via-first integration, the TSV is fabricated before

show abstract

Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Cited by 16 publications

References 28 publications

Microwave Monitoring of Atmospheric Corrosion of Interconnects

Microwave Monitoring of Atmospheric Corrosion of Interconnects

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Reliability Challenges Related to TSV Integration and 3-D Stacking

Contact Info

Product

Resources

About