Effect of temperature in selective buried oxide
            <scp>TFET</scp>
            in the presence of trap and its
            <scp>RF</scp>
            analysis

Ghosh, Puja; Bhowmick, Brinda

doi:10.1002/mmce.22269

Cited by 12 publications

(8 citation statements)

References 20 publications

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“…To evaluate linearity and distortion performance of the device [29,30], different parameters are calculated such as transconductance generation factor (TGF), second order voltage intercept point (VIP 2 ) [31], third order voltage intercept point (VIP 3 ) [31], current intercept point of third order (IIP 3 ), second and third order harmonic distortion (HD 2 and HD 3 ) and third order intermodulation distortion (IMD 3 ) [32]. The distortion and linear performance of the device depends upon the variables g m , g m2 , g m3, and I DS .…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, in order to have better linearity, g m should be higher and g m3 should be low. In the device for k = 25 at temperature 400 K [33] the value of IIP 3 [32] is highest, that means the device have better linearity performance. For k = 3 at temperature 200 K the value of IIP 3 is lowest and is plotted in 8 (c) and (d).…”

Section: ( ) ( )mentioning

confidence: 94%

“…IIP 3 is the ratio between first-order and the third-order harmonics, i.e., g m and g m3 [32]. Higher the value of IIP 3 better the linearity performance.…”

Section: ( ) ( )mentioning

confidence: 99%

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Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

Sachdeva

Bhushan²,

Bajaj³

et al. 2022

Eng. Res. Express

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Biosensors are critical part of today’s lifestyle. They have vast applications in medical industries making continuous advancement in the domain crucial. To further extend their utilities in this manuscript effect of variation in temperature on charge plasma based tunnel field effect transistor as biosensor is investigated. To investigate, device is simulated at 200K, 300K and 400K and various device, analog and linearity characteristics are examined. To create the cavity for accommodation of biomolecules, source electrode is extended. Analyzed device resulted in steepest subthreshold slope of 17.61mV/dec and 8.81mV/dec for κ=3 at T=200K. Device also has high ION sensitivity for entire temperature range. Due to promising characteristics, investigated biosensor can be used in future for detection of different biomolecules.

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Section: Resultsmentioning

confidence: 99%

Section: ( ) ( )mentioning

confidence: 94%

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Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

Sachdeva

Bhushan²,

Bajaj³

et al. 2022

Eng. Res. Express

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show abstract

“…Transconductance generation factor (TGF) is another crucial parameter to evaluate gain ( A V ) and cutoff frequency (

f_{T}

). The TGF variation with gate voltage is shown in Figure 5 and is expressed as TGF =

g_{m} / I_{DS} .

32 It measures the efficiency of a device in converting DC power into AC frequency and gain. The TGF value is high for HfO 2 spacer with 37.8 V −1 and least for hybrid spacer with 35.9 V −1 owing to the fact of higher

g_{m}

and lower

I_{DS}

.…”

Section: Analog/rf Performance Evaluation Of Multi‐fin Soi Fetmentioning

confidence: 99%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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“…According to Moor's Law for every eighteen months, there is a two-fold increase in the number of transistors. This device downscaling has advantages like less power consumption, high speed and reduction in cost [1][2][3][4][5][6][7]. The device dimensions are reduced in every successive technological node.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Neelam

Prithvi

2022

Silicon

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Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical con gurations of the NSFET. In this script, DC performance of 3D GAA NSFET is analyzed by varying the width, thickness of the device. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm, and 10 to 50 nm respectively to analyse the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (I ON ), off current (I OFF ), switching ratio (I ON /I OFF ), threshold voltage (V th ) and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43 o C to 127 o C to identify the temperature compensation point and is observed at V GS = 0.55 V and I D = 3.86 × 10 −6 A. Furthermore, the important process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses tell that, for sub -7 nm, the NSFET is a potential device for high performance and good logic applications.

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Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis

Cited by 12 publications

References 20 publications

Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

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