Effect of Substrate on “On‐Resistance” of a Power Metal‐Oxide Semiconductor Field‐Effect Transistor Device

Abstract

Motorola's high density "T" metal oxide semiconductor (HDTMOS TM ) structures are a new generation of power metal-oxide semiconductor field-effect transistor (MOSFET) devices with very high cell density. They offer generous current gain with low operating resistance, R DS(ON) , and cover a wide range of breakdown voltages. On-resistance is derived from the voltage between the drain and the source, V DS , when the device is switched on. For the power MOSFET, this characteristic is tested using a drain current (I D ) of Ϫ1 A and gate voltage (V GS ) of Ϫ2.7 V where R DS(ON) ϭ V DS /I D . Onresistance for power MOSFETs can be written as a summation of the various "subresistors" from which the device is composed 1where R src is the source resistance, R ch is the channel resistance, R A is the accumulation layer resistance, R J is the drift resistance between the channel regions, R D is the drift resistance, and R sub is the substrate resistance. For low-voltage devices (i.e., breakdown voltage less than 50 V), the source and drain regions can play a more significant role than in higher breakdown voltage devices. Note that contact resistance is absent in Eq. 1. ExperimentalThe 12.5 V power MOSFET devices were fabricated on 150 mm diam, silicon (100) substrates heavily boron doped to 10-30 m⍀ cm with a 4.5-5.5 m thick, 24-32 ⍀ cm epitaxial layer. In production lots, one supplier (A) had an average substrate resistivity of 18 m⍀ cm and the other supplier (B) had an average of 25 m⍀ cm. In one experiment, a split lot consisting of 12 substrates from each of the two suppliers was run through the production line. In another experiment, to test the effect of bulk microdefect (BMD) density, three substrates from each of the two suppliers plus another supplier (C) were pre-heat-treated for 2 h at 700ЊC prior to initial oxidation. These substrates and five standard nonpreheat substrates from each of the three suppliers were all processed through the device line in the same lot.After processing, all the substrates were back-ground to a thickness of 0.250 mm. Prior to application of the backmetal, a postgrind clean was used to remove the grinding contaminants. The postgrind clean and backmetal processes were also investigated to see the impact of back side contact on R DS(ON) . One lot with supplier B substrates was split twice. The first split was at back side clean where half the lot received HF dip and the other half received the SEZ spin etch process. The SEZ etching process consisted of a short stress relief etch, an 80 s mix etch of HF ϩ HNO 3 ϩ H 2 SO 4 , and an HF etch. The second split was at back side metal where half the lot received TiNiAg and the other half received an aluminum metal layer prior to the TiNiAg backmetal. The back side metals of selected wafers were stripped using an H 2 SO 4 (4 parts) plus H 2 O 2 (1 part) solution. A state-of-the-art magnetic secondary ion mass spectrometry (SIMS) instrument, Cameca IMS-6f, was employed to obtain an aluminum depth profile in the back side of the stripped silicon waf...

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