Effect of Some Device Parameters on the Transient Characteristics of Nanoscale CMOS Inverters

Abstract

Rigorous mathematical formulation of digital circuits, although accurate, consumes simulation time of a circuit designer who wishes to have a quick investigation of the effect of various device parameters on the electrical response of a circuit. This paper uses simple yet efficient method to calculate the average resistance of the transistors for finding the RC time constant and thereby the transient analysis of CMOS inverter circuits. This method minimizes the computation time and reproduces the reported results. We have investigated the effect of variation of different device parameters such as width, oxide thickness, length etc. on the transient analysis of inverters. Computations were carried out for strained/unstrained planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and cylindrical gate-all-around (GAA) based CMOS inverters. Voltage-transfer characteristics (VTC) have also been plotted. Quantum effects have been incorporated for gate-all-around (GAA) MOSFETs based inverters.

Monitor amb control strategies to reduce the impact of process variations in digital circuits

“…For this reason, the author in [40] suggests to scale down T OX no further than 2 nm, which corresponds to 10 atomic layers. Variations in 1 or 2 atomic layers of T OX cause significant V T H variations that leads to leakage and performance variability [41]. This effect is known as Interface Roughness (IR).…”