Effect of Oxide on Trench Edge Defect Formation in Ion-Implanted Silicon

Abstract

An investigation of the defects that form near oxide-filled trenches during solid-phase epitaxy of amorphous silicon produced by ion implantation was conducted. It was observed that defects form near the trench edge after recrystallization. Defect formation resulted from pinning of the initial amorphous/crystalline interface at the trench edge and regrowth proceeded until triangular amorphous regions bound by the surface, trench, and ͑111͒ plane were formed. Regrowth of the triangular regions then proceeded along the ͓111͔ direction and was highly defective after recrystallization. Annealing of specimens with oxide-free trenches produced smaller defective regions compared to oxide-filled trenches. © 2007 The Electrochemical Society. ͓DOI: 10.1149/1.2719597͔ All rights reserved.Manuscript submitted December 20, 2006; revised manuscript received February 7, 2007. Available electronically March 28, 2007. It has been known that stress from oxide ͑SiO 2 ͒ trench structures in ion-implanted silicon ͑Si͒ wafers can lead to the formation of defects near trench edges, which may cause device degradation or failure.1-3 These defects typically form during high-temperature processing but may also occur during solid-phase epitaxy ͑SPE͒ of amorphous ͑␣͒ Si. It is known that SPE in bulk Si can lead to the formation of ͕111͖ stacking faults as well as other secondary defects. 4 More relevantly, regrowth of two-dimensional ␣-Si regions via simultaneous SPE of two orthogonal fronts with different crystal orientations in patterned wafers can produce defects near the mask-edge. [5][6][7] However, the formation of defects during SPE near trench structures is not well understood. In the case of high-dose arsenic ͑As͒ implantation well in excess of solubility, trench-edge defects were observed as a result of regrowth interface pinning during SPE.8 Furthermore, As + -implantation is known to cause secondary defect formation at the projected range of implantation, and it is unclear whether the implanted species affects trench-edge defect formation.9,10 Another explanation for trench-edge defects is the migration of point defects to regions of high stress generated by patterned structures, but this not thought to be related to SPE.11 Thus, the goal of this study is to investigate the formation of trench-edge defects during SPE in Si wafers amorphized by Si + implantation. For this study, 300 mm ͑001͒ wafers were patterned with SiO 2 -filled trenches ϳ400 nm deep. After patterning, the wafers were implanted with Si + at energies of 10-80 keV and doses of 1 ϫ 10 15 to 1 ϫ 10 16 cm −2 . This produced ␣-Si layer depths ranging from 20 to 160 nm. Anneals were performed at 700 or 950°C using rapid thermal annealing ͑RTA͒. All anneals were preceded by a 10 s soak at 600°C. Transmission electron microscopy ͑TEM͒ was used to image ␣-Si regrowth in the vicinity of trench edges. Both crosssectional TEM ͑XTEM͒ and plan-view TEM ͑PTEM͒ were used for this study. Imaging was performed using weak-beam dark-field ͑WBDF͒ or on-axis bright-field ͑BF͒ con...

Defective Solid-Phase Epitaxial Growth of Si

“…In fact, it was previously shown that the SPEG process in similar structures on (001) wafers results in faceting of the growth interface along the same {111} plane with the growth interface pinned at the initial point of contact with the SiO x -filled trench; this results in a triangular region of α-Si bound by the SiO x -filled trench, the wafer surface, and the {111} plane (Burbure et al, 2007). It should also be noted that similar faceting was observed for SPEG in the vicinity of SiO x -filled trenches for wafer orientations other than (001) (Saenger et al, 2007a).…”

Solid-phase epitaxial growth of (111)-oriented Si film on InGaO3(ZnO)5 buffer layer

“…Conventional (111)-oriented solid-phase epitaxial growth [15][16][17][18] has been achieved by utilizing latticematched epitaxy during thin-film growth as long as the lattice misfit is less than 8%. On the other hand, Narayan et.al [19,20] has showed that a large lattice misfit relative to the substrate can still grow epitaxial layers, which is called 'domain matching epitaxy (DME)', where integral multiples of the lattice constants make a good lattice matching between the substrate and the over-grown layer [21].…”

“…After that, a 150 nm thick Si layer was deposited by physical vapor deposition (PVD) at 450°C. Then the sample is further annealed at 950°C [18] in an atmospheric electric furnace to crystallize the Si film. The temperature was same as a previous paper which reports (111) epitaxial growth of Si on Si seed substrate [18].…”

“…Then the sample is further annealed at 950°C [18] in an atmospheric electric furnace to crystallize the Si film. The temperature was same as a previous paper which reports (111) epitaxial growth of Si on Si seed substrate [18]. A Philips XL50 SEM equipped with an EDAX-EDAX-TSL Crystal EBSD system was used for EBSD analyses.…”

Suppression of transient enhanced diffusion in sub-micron patterned silicon template by dislocation loops formation

“…Formation of extended defects near the ion implantation mask edges after dopant annealing has been reported. [10][11][12] The types and spatial distribution of extended defects depends on the length scales of the ion implantation edges, and the ion implantation doses. In particular, for silicon amorphized with high dose (1x 10 15 cm −2 ∼ 1x 10 16 cm −2 ) self-implantation, dislocation loops were frequently observed after solid phase epitaxial regrowth (SPER).…”