Effect of noise on the resolution of CMOS analog readout systems for microstrip and pixel detectors

Chang, Zhihua; Sansen, Willy

doi:10.1016/0168-9002(91)90156-k

Cited by 34 publications

(14 citation statements)

References 11 publications

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“…A folded cascode architecture is commonly used in the implementation of the preamplifier, mainly because of its low input capacitance [6]- [14]. On the other hand a current mode structure could be an attractive alternative to the more typical voltage mode one, since the Abstract Alternative current mode charge sensitive amplifier (CSA) topology and related methodology for use as preamplification block in radiation detection read out front end IC systems is proposed.…”

Section: Proposed Methodology -Architecturementioning

confidence: 99%

“…This offers all the advantages of an integrated solution like low power consumption small area and weight. However, the most crucial motivation is that the implementation of readout electronics and semiconductor detectors onto the same chip offers enhanced detection sensitivity thanks to improved noise performances [1]- [6]. Placing the very first stage of the front-end circuit close to the detector electrode reduces the amount of material and complexity in the active detection area and minimizes connection-related stray capacitances.…”

Section: Proposed Methodology -Architecturementioning

confidence: 99%

See 1 more Smart Citation

Current mode charge sensitive amplifying technique providing noise performance independent of the radiation detector capacitance

Noulis

Siskos

Sarrabayrouse

et al. 2009

2009 3rd International Workshop on Advances in Sensors and Interfaces

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Section: Proposed Methodology -Architecturementioning

confidence: 99%

Section: Proposed Methodology -Architecturementioning

confidence: 99%

Current mode charge sensitive amplifying technique providing noise performance independent of the radiation detector capacitance

Noulis

Siskos

Sarrabayrouse

et al. 2009

2009 3rd International Workshop on Advances in Sensors and Interfaces

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“…A current noise is associated with the detector leakage current, the detector bias resistance and the feedback resistor R fed in the CSA, so the power spectral density is given by In order to find the ENC of a detector system one needs to calculate the noise rms value at the shaper output. Knowing the charge gain of the system the equivalent noise charge can be expressed as [4,5] …”

Section: Charge Sensitive Amplifier and Noise Sourcesmentioning

confidence: 99%

Design of low noise charge amplifier in sub-micron technology for fast shaping time

Gryboś

Idzik

Skoczeń

2006

Analog Integr Circ Sig Process

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A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13 µm to 0.8 µm and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.

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“…These parameters can be extracted from HSPICE simulations for MOS transistors operating in strong inversion (in our case the BSIM3v3 transistor model was used). The slope factor was calculated as: (13) while the we calculated from formula (4) using total gate capacitance obtained from HSPICE simulations. The values of and parameters, calculated as described above, are shown in Table I for four CMOS technologies considered in this paper.…”

Section: Simplified Ekv Modelmentioning

confidence: 99%

Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

Gryboś

Idzik

Maj

2007

IEEE Trans. Nucl. Sci.

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The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor operating in the moderate inversion region is discussed. The MOS transistor operation in the moderate inversion region becomes especially important in multichannel readout systems where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the voltage noise of the input MOS transistor. We carried out noise minimization for such a CSA, searching for an optimum input transistor width. The analyses were made using a simplified EKV model and were compared to HSPICE simulations using a BSIM3v3 model. We considered several CMOS technology generations with minimum transistor gate length ranging from 0.13 m to 0.8 m. We studied the sensitivity of ENC to the input transistor width, and propose a simple formula to estimate the optimum transistor width, which is valid in a wide current density range.Index Terms-Charge sensitive amplifier, CMOS.

show abstract

Effect of noise on the resolution of CMOS analog readout systems for microstrip and pixel detectors

Cited by 34 publications

References 11 publications

Current mode charge sensitive amplifying technique providing noise performance independent of the radiation detector capacitance

Current mode charge sensitive amplifying technique providing noise performance independent of the radiation detector capacitance

Design of low noise charge amplifier in sub-micron technology for fast shaping time

Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

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