Effect of Nanotopography in Direct Wafer Bonding: Modeling and Measurements

Abstract

Abstract-Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.Index Terms-Direct bonding, microelectromechanical systems (MEMS), nanotopography, silicon-on-insulator (SOI), wafer bonding.

Studies on low-temperature direct bonding of VUV, VUV/O3 and O2 plasma pretreated cyclo-olefin polymer

“…The R a and R ms decreased after VUV and VUV/O 3 treatments. The decrease of the surface roughness can assist the room temperature bonding because the two surfaces contact easier [40][41][42][43][44]. The decreases of the roughness on the VUV and VUV/O 3 treated COPs seem to be originated with the degradation of COP surfaces, as reported in case of PMMA [23].…”

Role of wafer geometry in wafer chucking

“…Both wafers in this set have a wafer-scale bow with an amplitude of tens of micrometers, as would be caused by a residually stressed film on one surface, as well as features at shorter spatial wavelengths that fall in the NT regime. 13 Specifically, both wafers in Fig. 4 have a wafer-scale bow with amplitude of 40 μm, but have different NT: wafer (a) has a wavelength of 10 mm and amplitude of 50 nm, while wafer (b) has a wavelength of 10 mm and amplitude of 100 nm.…”

Three‐Dimensional (3D) Integration

“…For the characterization of 3D integration and wafer-level packaging (WLP) approaches such as the use of redistribution layers, wafer-level planarization requirements have not been explored to the level required for the integration of high-yield bonding processes other than direct silicon bonding [101][102][103]. These issues are particularly problematic for patterned wafer-level 3D technology platforms.…”

“…15.13 shows a bonding map for silicon wafer bonding: combinations of topography and spatial wavelength that fall below the traces will bond; those above the traces will produce voids [101]. This and further work by Turner et al have explored parameters for direct wafer bonding under clamped conditions [107], addressed wafer bow and etch pattern considerations [108], as well as nanoscale roughness considerations [101]. This work shows that Step heights below the curve will be closed by surface forces; those above the curve will generate voids in the bonding interface.…”