Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance

Abstract

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Mitigating mask roughness via pupil filtering

“…It was reported that the LWR started to impact the device performance for critical dimension (CD) values less than 85 nm. It was also found that the off-state leakage current significantly increased when LWR was larger than 10 nm [25].…”

“…For instance, the effect of line width roughness (LWR) on sub-100 nm NMOS device electrical performance was investigated experimentally by fabricating 80 nm node transistors of varying gate length, width, and roughness values by [25]. It was reported that the LWR started to impact the device performance for critical dimension (CD) values less than 85 nm.…”

Line edge roughness and intrinsic bias for two methacrylate polymer resist systems

“…These intra transistor effects can result in greater amounts of leakage. [1][2][3][4][5][6][7][8][9][10][11] Second, roughness adds variability in the fabrication process, leading to CD variations across the chip that make transistor matching much more difficult. Large distributions in transistor gate length can limit the overall speed performance of a device.…”

Effects of lithography non-uniformity on device electrical behavior. Simple stochastic modeling of material and process effects on device performance

“…Simple statistical analysis based on 2D modeling of transistor performance has shown that the gate patterns without the appropriate LWR control may cause severe fluctuations in device parameters and performance, especially in the nanometer scaled MOSFET technologies, resulting in a negative average threshold voltage shift, a sub-threshold slope degradation, an unrealistic effective channel length extraction and an exponential increase in off-state leakage current [1][2][3][4][5][6][7][8][9].…”