Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Non-Intrusive Methodologies for Characterization of Bias Temperature Instability in SiC Power MOSFETs

“…This agrees with the literature, which reports an increased VTH shift with stress voltage level [2], [19], [20] A significant observation already reported in [34] is the existence of the phenomenon of dip-and-rebound at high gate voltage stresses (35 V) in the evaluated planar SiC MOSFET. This phenomenon was also observed for Si MOSFETs [36], at gate stress levels of 65 V.…”

“…The reduction of VSD when VGS=0 V during both stages of the stress sequence indicates that VTH reduces after the gate bias removal. The dip-and-rebound, as explained in [36], is caused by the different contribution of the interface trapped charges, which cause an increase of VTH, and the oxide trapped charges, which reduce VTH. This stress level is higher than the recommended gate voltage and may not represent the real shift in real application, however these type of accelerated stress tests can be relevant for the evaluation of the robustness and reliability of the gate oxide.…”

Characterization of BTI in SiC MOSFETs Using Third Quadrant Characteristics

“…10 show, during the initial phase of the 35 V pulsed stress, there is an initial VSD reduction indicating a reduction of VTH followed by the expected increase of VSD for PBTI during the final stage of the pulsed stress. This phenomenon of dip and rebound was already described in [7] for Si MOSFETs and is caused by the different contribution of the oxide trapped charges (decreasing VTH) and the interface trapped charges (increasing VTH) during the different stages of the stress. This is defined by (2) [7], where Not is the stress-induced change in the oxide trapped charge, Nit is stress-induced change in the interface trapped charge and COX is the specific gate oxide capacitance.…”

“…This phenomenon of dip and rebound was already described in [7] for Si MOSFETs and is caused by the different contribution of the oxide trapped charges (decreasing VTH) and the interface trapped charges (increasing VTH) during the different stages of the stress. This is defined by (2) [7], where Not is the stress-induced change in the oxide trapped charge, Nit is stress-induced change in the interface trapped charge and COX is the specific gate oxide capacitance. In a traditional long duration stress, this peculiar feature of the highly accelerated stress test would not be captured, hence the benefits of using the 3 rd quadrant characteristics for assessing the impact of the BTI in SiC MOSFETs.…”

Bias temperature instability and condition monitoring in SiC power MOSFETs

“…Very recent work on this topic has been presented in [10] for Si power MOSFETs. In this section, the onstate resistance and the 3 rd quadrant characteristics are evaluated as indicators of gate oxide degradation for SiC MOSFETs.…”